A Compact Implementation of AES S‐Box Using Evolutionary Algorithm

Liu, Yaoping; Wu, Ning; Zhang, Xiaoqiang; Fang, Zhou; Feng, Guorui

doi:10.1049/cje.2016.08.021

Cited by 10 publications

(5 citation statements)

References 16 publications

(45 reference statements)

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“…Table 3 shows the DC synthesis results and the theoretical estimation results of Critical Path Delay (CPD). Note that the delay equivalent relationship between logic gates used to estimate CPD and equivalent CPD in Table 3 refers to the standard in [13]. The specific equivalent relationship is listed in Table 4.…”

Section: Experiments Results and Performance Evaluationmentioning

confidence: 99%

“…However, the implementation performance of S-box based on composite fields is related to the selection of low-order fields and their representation basis. To address this issue, several scholars have conducted extensive research on the selection of isomorphic matrix or polynomial basis and have proposed various optimization schemes of S-box [10] [11] [12] [13]. R. Ueno et al [14] used different polynomial basis and Galois field arithmetic to optimize the inversion circuit, and proposed an efficient and compact S-box architecture.…”

Section: Introductionmentioning

confidence: 99%

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A High Efficiency Hardware Implementation of S-Boxes Based on Composite Field for Advanced Encryption Standard

Wang,

Bin,

Zhu

et al. 2024

JCC

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The SubBytes (S-box) transformation is the most crucial operation in the AES algorithm, significantly impacting the implementation performance of AES chips. To design a high-performance S-box, a segmented optimization implementation of the S-box is proposed based on the composite field inverse operation in this paper. This proposed S-box implementation is modeled using Verilog language and synthesized using Design Complier software under the premise of ensuring the correctness of the simulation result. The synthesis results show that, compared to several current S-box implementation schemes, the proposed implementation of the S-box significantly reduces the area overhead and critical path delay, then gets higher hardware efficiency. This provides strong support for realizing efficient and compact S-box ASIC designs.

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Section: Experiments Results and Performance Evaluationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A High Efficiency Hardware Implementation of S-Boxes Based on Composite Field for Advanced Encryption Standard

Wang,

Bin,

Zhu

et al. 2024

JCC

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show abstract

“…The comparative algorithms are described in brief here. The works [7], [8], and [10] use the normal basis to establish the tower field and then map the elements of the Galois field GF (2 8 ) to this field. By contrast, the proposed work, [9], [11], and [19] use the composite field representation of GF((2 4 ) 2 ) to construct the S-box.…”

Section: Implementation Resultsmentioning

confidence: 99%

VLSI Architecture of S-Box With High Area Efficiency Based on Composite Field Arithmetic

et al. 2022

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This work aims at optimizing the hardware implementation of the SubBytes and inverse SubBytes operations in the advanced encryption standard (AES). To this, the composite field arithmetic (CFA) is employed to optimize all building blocks in S-box (and inverse S-box) of SubBytes (and inverse SubBytes) transformation. A joint design of S-box and inverse S-box is also proposed to further enhance the area efficiency. Specifically, the area of multiplier in the Galois composite field, GF((2 2 ) 2 ), is reduced. The squaring and multiplication with constant λ in GF((2 2 ) 2 ) are combined and optimized as well. Moreover, the multiplicative inversion in GF((2 2 ) 2 ) is manually optimized. Furthermore, the S-box and inverse Sbox are combined and optimized using the pre_processing and post_processing modules. To increase the throughput, a balanced and pipelined architecture is derived. Using the proposed architecture, a throughput of 5.79 Gbps for the S-box can be achieved on Virtex-6 XC6VLX240T and 10% better than the conventional work. According to the ASIC implementation result, the proposed design can still achieve the highest area efficiency and approximately 30% better than conventional works using TSMC 90nm process.INDEX TERMS Advanced encryption standard (AES), Composite field arithmetic (CFA), S-box, VLSI architecture.

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“…As shown in Fig. 1, point A belongs to subspace ψ l , points B and C belong to subspace ψ 2 , and point D belongs to subspace ψ 3 . Points E, F , and G belong to subspace ψ 4 , and point H belongs to subspace ψ 5 .…”

Section: Spatial-based Divisionmentioning

confidence: 99%

“…It is common to encounter optimization problems in practice where multiple conflicting criteria need to be optimized simultaneously [ 1 ] ; therefore, finding a satisfactory solution quickly and accurately is an extremely challenging task [ 2 ] . The Multi‐objective evolutionary algorithm (MOEA) is an intelligent optimization based on the population searching way [ 3,4 ] . The vector evaluated genetic algorithm is a milestone for evolutionary computing [ 5 ] .…”

Section: Introductionmentioning

confidence: 99%

A Many‐Objective Evolutionary Algorithm with Spatial Division and Angle Culling Strategy

Wang

Yang

Tian

et al. 2021

Chinese J of Electronics

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In a specific project, how to find a reasonable balance between a plurality of objectives and their optimal solutions has always been an important aspect for researchers. As a trade off between fast convergence and a rich diversity, a Many‐objective evolutionary algorithm based on a spatial division and angle‐culling strategy (MaOEA‐SDAC) is proposed. In the reorganization stage, a restricted matching selection can enhance the reproductivity. In the environment selection stage, a space division and angle‐based elimination strategy can effectively improve the convergence and diversity imbalance of its solution set. Through detailed experiments and a comparative analysis of the proposed MaOEA‐SDAC with five other state‐of‐the‐art algorithms on classical benchmark problems, the effectiveness of MaOEA‐SDAC in solving high‐dimensional optimization problems has been verified.

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A Compact Implementation of AES S‐Box Using Evolutionary Algorithm

Cited by 10 publications

References 16 publications

A High Efficiency Hardware Implementation of S-Boxes Based on Composite Field for Advanced Encryption Standard

A High Efficiency Hardware Implementation of S-Boxes Based on Composite Field for Advanced Encryption Standard

VLSI Architecture of S-Box With High Area Efficiency Based on Composite Field Arithmetic

A Many‐Objective Evolutionary Algorithm with Spatial Division and Angle Culling Strategy

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