A Compact FPGA‐Based Accelerator for Curve‐Based Cryptography in Wireless Sensor Networks

Abstract

The main topic of this paper is low-cost public key cryptography in wireless sensor nodes. Security in embedded systems, for example, in sensor nodes based on field programmable gate array (FPGA), demands low cost but still efficient solutions. Sensor nodes are key elements in the Internet of Things paradigm, and their security is a crucial requirement for critical applications in sectors such as military, health, and industry. To address these security requirements under the restrictions imposed by the available computing resources of sensor nodes, this paper presents a low-area FPGA-prototyped hardware accelerator for scalar multiplication, the most costly operation in elliptic curve cryptography (ECC). This cryptoengine is provided as an enabler of robust cryptography for security services in the IoT, such as confidentiality and authentication. The compact property in the proposed hardware design is achieved by implementing a novel digit-by-digit computing approach applied at the finite field and curve level algorithms, in addition to hardware reusing, the use of embedded memory blocks in modern FPGAs, and a simpler control logic. Our hardware design targets elliptic curves defined over binary fields generated by trinomials, uses fewer area resources than other FPGA approaches, and is faster than software counterparts. Our ECC hardware accelerator was validated under a hardware/software codesign of the Diffie-Hellman key exchange protocol (ECDH) deployed in the IoT MicroZed FPGA board. For a scalar multiplication in the sect233 curve, our design requires 1170 FPGA slices and completes the computation in 128820 clock cycles (at 135.31 MHz), with an efficiency of 0.209 kbps/slice. In the codesign, the ECDH protocol is executed in 4.1 ms, 17 times faster than a MIRACL software implementation running on the embedded processor Cortex A9 in the MicroZed. The FPGA-based accelerator for binary ECC presented in this work is the one with the least amount of hardware resources compared to other FPGA designs in the literature.

Secured V2x Communication Using Optimized Prime Field Ecc Architecture

“…The only constraints that the designs reported in [15,18] is that the acceleration or implementation of ECPM computations. Similar to this, the designs reported in [19,20] are limited by the enormous computation times.…”

“…Multiple modular multipliers are employed in [18] to reduce latency. In [19,20], the coprocessor designs for ECDH-based key agreement are discussed. In order to accomplish flexibility, a coprocessor involves the integration of an FPGA with a host device (such as a microcontroller or processor) without taking into account the performance factors [21].…”

“…In order to save size and power consumption, [19] offloads the ECDH operations to an FPGA using a high-level synthesis (HLS) technique. A low-cost ECC hardware accelerator architecture on FPGA is given in [20] for wireless sensor nodes. As a result, it is essential to provide a high-speed, low-resource ECC Processor architecture for key agreement.…”

Area-Efficient Realization of Binary Elliptic Curve Point Multiplication Processor for Cryptographic Applications

“…Concerning the aforementioned selections, several PM ECC designs exist in the literature; however, we preferred to include only those implemented and optimized for area-efficient realizations. Examples of the most recent hardware accelerators are available in [12][13][14][15][16][17][18]. A two-stage pipelined PM architecture of ECC is described in [12], where pipelining is utilized to decrease the critical path delay and carefully schedule the computations associated with PA and PD to reduce the number of clock cycles required; these two characteristics combine to decrease the time needed for a single PM operation, and the minimum utilization of area results in a higher throughput/area ratio.…”

Performance Improvement of SIMD Processor for High-Speed end Devices in IoT Operation Based on Reversible Logic with Hybrid Adder Configuration

“…As these nodes are often set at locations without significant networking or power structures, such as on farms and forests, many sensor nodes are designed to be highly resource-efficient to operate arbitrarily time-efficient automatically. For example, they may work for quite a long time on a little battery [6,7] and convey through slow and low-power communication networks [8,9].…”