A Compact Chopper Stabilized Δ-ΔΣ Neural Readout IC With Input Impedance Boosting

Abstract

This paper presents a scalable neural recording analog front-end architecture enabling simultaneous acquisition of action potentials, local field potentials, electrode DC offsets and stimulation artifacts without saturation. By combining a DC-coupled -architecture with new bootstrapping and chopping schemes, the proposed readout IC achieves an area of 0.0077 mm 2 per channel, an input-referred noise of 5.53 ± 0.36 µV rms in the action potential band and 2.88 ± 0.18 µV rms in the local field potential band, a dynamic range of 77 dB, an electrode-DC-offset tolerance of ±70 mV and an input impedance of 663 M . To validate this neural readout architecture, we fabricated a 16-channel proof of-concept IC and validated it in an in vitro setting, demonstrating the capability to record extracellular signals even when using small, high-impedance electrodes. Because of the small area achieved, this architecture can be used to implement ultra-high-density neural probes for large-scale electrophysiology.

A 16-µW 10-kHz BW incremental <i>ΔΣ</i> ADC with automatic EDO canceling for implantable neural recording

“…However, due to its complex signal chain, recording chips that employ this architecture often require significant power consumption and area. The second architecture of recording chips omits the low noise amplifiers and directly quantizes neural signals using a low noise ADC [20,21,22,23,24,25,26,27,28,29,30]. Due to its simplified signal processing chain, this architecture can often achieve a low single-channel area [23,24,25,26,27], or a large input range with low power consumption [28,29,30], making it highly promising for future research.…”

“…The second architecture of recording chips omits the low noise amplifiers and directly quantizes neural signals using a low noise ADC [20,21,22,23,24,25,26,27,28,29,30]. Due to its simplified signal processing chain, this architecture can often achieve a low single-channel area [23,24,25,26,27], or a large input range with low power consumption [28,29,30], making it highly promising for future research. [25] proposed a DC coupled input, two-step quantization incremental ΔΣ ADC that exhibits superior performance.…”

A 12 μW 10 kHz BW 58.9 dB SNDR AC-Coupled Incremental ADC for Neural Recording

“…T ADCs are mostly oversampling-type ADCs, utilizing noise shaping to improve accu Refs. [25][26][27] adopted the Δ-ΔΣ architecture, which adds a differentiator before the ventional ΔΣ to eliminate EDO by subtracting adjacent input signals. Refs.…”

“…The remaining sections of this paper are organ as follows: Section 2 provides a mathematical analysis of the working principle of A However, as the number of integrated channels increases, the first approach becomes limited by the complex signal processing chain, which restricts the area of the recording unit circuit. To address this issue, researchers have proposed a second solution, as shown in Figure 1b, which directly quantifies neural signals using low-noise ADC [24][25][26][27][28][29][30][31][32]. These ADCs are mostly oversampling-type ADCs, utilizing noise shaping to improve accuracy.…”

“…Refs. [25][26][27] adopted the ∆-∆Σ architecture, which adds a differentiator before the conventional ∆Σ to eliminate EDO by subtracting adjacent input signals. Refs.…”