A compact carry-save multiplier architecture and its applications

Abstract

Carry-save arithmetic based architectures are becoming popular in VLSI designs. However, few designs are available for 2's complement carry-save multipliers. The carrysave outputs from conventional 2's complement multiplie r~ are not in legitimate carry-save form. This leads to errors if carry-save manipulations, such as, saturations, sign-extension etc are used. In this paper, a pure carrysave multiplier design i s presented. The architecture is compact and regular leading to ease in VLSI implementation. This architecture is extended to design a carry-save mirltiplier/acciimulator. By manipulating the partial product additions a row of adders are saved. Since multipliers form the basic building blocks of any signal processing ASIC design, this leads to large savings in chip area and power dissipation. Application of this design to equalizers and other signal processing blocks is also presented. I IntroductionThere is a flurry of activity going on right now in the area of general purpose processors, DSP processors, embedded processors, ASIC core libraries, high-performance ASIC chips etc. Area, speed and power dissipation are crucial parameters for competitive advantage. Even though advances in technology are improving the computation speed rapidly, there is demand for faster chips which consume low power. In this paper we discuss carry-save arithmetic representations which will help reduce the computation speed and lead to reduction in power dissipation. We present compact implementations of multipliers and adders which are the basic building blocks for any processing system.The two's complement binary number system is an accepted standard in all digital computing. Recently, there has been a surge in interest in non-conventional number systems such as redundant number system [1],[2],[3] carrysave arithmetic[4], residue number system [5],[6], and logarithmic number system [7],[8]. The different number systems are suitable for different types of arithmetic operations. The main attraction of carry-save and redundantnumber arithmetic is the low-delay addition operation. In a binary adder the carry has to ripple through all the adders giving a delay proportional to the wordlength W . Binary carry look-ahead adder can reduce this delay but the overhead in terms of area and power is high. A number of techniques have been explored recently to get around the carry-ripple problem [9],[10]. In carry-save and redundant arithmetic, this carry-ripple is altogether avoided. Hence these architectures are faster and consume less area and power. In fact the power dissipation is significantly lower since the carry-ripple part consumes a large part of the power disspation. Redundant number system based arithmetic operators were used in DEC-ALPHA processor chip [Ill, MIPS processor [12] and other recent designs [13].Carry-save arithmetic is used in a number of chips within Lucent Technologies including a recent Q A M demodulator chip. However, a better understanding of the intricacies of carry-save arithmetic would lead to a more w...