A Compact Adderless Feed-Forward Incremental Delta Sigma with Multiple Global References for CMOS Image Sensors

Abstract

This paper presents an adderless feed-forward incremental ΔΣ (IΔΣ) with asynchronous SAR (ASAR) that removes the need for in-column calibration by using global references, eliminates an additional summing amplifier and reduces the conversion time by using a multi-bit ASAR quantizer. The proposed IΔΣ ADC is designed in 40nm CMOS technology and is laid out compactly in a 5 μm x 466 μm column. According to post-layout simulations, the ADC achieves an input-referred noise of 85 μVrms, a conversion time of 3.2 μs (with DCDS) and a power consumption of 230 μW. This results in a Walden FoMW of 234 fJ/conv.step and a FoMA = FoMW x AADC of 0.54 fJ.mm2/conv.step, which demonstrates the feasibility of using the proposed architecture in CMOS image sensors.