A Communication-Centric Approach for Designing Flexible DNN Accelerators

Kwon, Hyoukjun; Samajdar, Ananda; Krishna, Tushar

doi:10.1109/mm.2018.2877289

Cited by 14 publications

(12 citation statements)

References 13 publications

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“…For this reason, the third pillar of our envisaged architecture is taking a communication-centric design approach. This is a philosophy that has been applied to endow DNN accelerators with certain flexibility [33], [177], [178] or to optimize distributed learning [179]. In our case, we propose the use of a reconfigurable interconnect fabric among the PEs to adapt the hardware to the underlying graph connectivity or, in other words, to the optimal dataflow that may vary across layers, partitions, or graphs.…”

Section: Communication-centric Designmentioning

confidence: 99%

Computing Graph Neural Networks: A Survey from Algorithms to Accelerators

et al. 2021

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Graph Neural Networks (GNNs) have exploded onto the machine learning scene in recent years owing to their capability to model and learn from graph-structured data. Such an ability has strong implications in a wide variety of fields whose data are inherently relational, for which conventional neural networks do not perform well. Indeed, as recent reviews can attest, research in the area of GNNs has grown rapidly and has lead to the development of a variety of GNN algorithm variants as well as to the exploration of ground-breaking applications in chemistry, neurology, electronics, or communication networks, among others. At the current stage research, however, the efficient processing of GNNs is still an open challenge for several reasons. Besides of their novelty, GNNs are hard to compute due to their dependence on the input graph, their combination of dense and very sparse operations, or the need to scale to huge graphs in some applications. In this context, this article aims to make two main contributions. On the one hand, a review of the field of GNNs is presented from the perspective of computing. This includes a brief tutorial on the GNN fundamentals, an overview of the evolution of the field in the last decade, and a summary of operations carried out in the multiple phases of different GNN algorithm variants. On the other hand, an in-depth analysis of current software and hardware acceleration schemes is provided, from which a hardware-software, graph-aware, and communication-centric vision for GNN accelerators is distilled.

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Section: Communication-centric Designmentioning

confidence: 99%

Computing Graph Neural Networks: A Survey from Algorithms to Accelerators

et al. 2021

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“…General dataflow for a CNN accelerator can be categorized into four types: Weight Stationary (WS), Input Stationary (IS), Output Stationary (OS), and Row Stationary (RS), based on the taxonomy and terminology proposed in [42]. Kwon et al propose MEARI, i.e., a type of flexible dataflow mapping for DNN with reconfigurable interconnects [25,27]. Chen et al present a row-stationary dataflow adapting to their spatial architecture designed for CNNs processing [9].…”

Section: Dataflowmentioning

confidence: 99%

Domino: A Tailored Network-on-Chip Architecture to Enable Highly Localized Inter- and Intra-Memory DNN Computing

Zhou¹,

Yangshuo²,

Xiao³

et al. 2021

Preprint

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The ever-increasing computation complexity of fast-growing Deep Neural Networks (DNNs) has requested new computing paradigms to overcome the memory wall in conventional Von Neumann computing architectures. The emerging Computing-In-Memory (CIM) architecture has been a promising candidate to accelerate neural network computing. However, the data movement between CIM arrays may still dominate the total power consumption in conventional designs. This paper proposes a flexible CIM processor architecture named Domino to enable stream computing and local data access to significantly reduce the data movement energy. Meanwhile, Domino employs tailored distributed instruction scheduling within Network-on-Chip (NoC) to implement inter-memory-computing and attain mapping flexibility. The evaluation with prevailing CNN models shows that Domino achieves 1.15-to-9.49× power efficiency over several stateof-the-art CIM accelerators and improves the throughput by 1.57-to-12.96×.

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“…MAERI [67], [69] is a DNN accelerator design with a set of configurable building blocks consisting of multiply and adder engines that can be configured with tiny switches. This new modular design can support various dataflows of arbitrary DNNs and map them successfully on accelerator elements.…”

Section: Reconfigurable Interconnectsmentioning

confidence: 99%

An Overview of Efficient Interconnection Networks for Deep Neural Network Accelerators

Nabavinejad

Baharloo

Chen

et al. 2020

IEEE J. Emerg. Sel. Topics Circuits Syst.

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Deep Neural Networks (DNNs) have shown significant advantages in many domains, such as pattern recognition, prediction, and control optimization. The edge computing demand in the Internet-of-Things (IoTs) era has motivated many kinds of computing platforms to accelerate DNN operations. However, due to the massive parallel processing, the performance of the current large-scale artificial neural network is often limited by the huge communication overheads and storage requirements. As a result, efficient interconnection and data movement mechanisms for future on-chip artificial intelligence (AI) accelerators are worthy of study. Currently, a large body of research aims to find an efficient on-chip interconnection to achieve low-power and high-bandwidth DNN computing. This paper provides a comprehensive investigation of the recent advances in efficient on-chip interconnection and design methodology of the DNN accelerator design. First, we provide an overview of the different interconnection methods on the DNN accelerator. Then, the interconnection methods on the non-ASIC DNN accelerator will be discussed. On the other hand, with the flexible interconnection, the DNN accelerator can support different computing flow, which increases the computing flexibility. With this motivation, reconfigurable DNN computing with flexible on-chip interconnection will be investigated in this paper. Finally, we investigate the emerging interconnection technologies (e.g., in/near-memory processing) for the DNN accelerator design. This paper systematically investigates the interconnection networks in modern DNN accelerator designs. With this article, the readers are able to: 1) understand

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A Communication-Centric Approach for Designing Flexible DNN Accelerators

Cited by 14 publications

References 13 publications

Computing Graph Neural Networks: A Survey from Algorithms to Accelerators

Computing Graph Neural Networks: A Survey from Algorithms to Accelerators

Domino: A Tailored Network-on-Chip Architecture to Enable Highly Localized Inter- and Intra-Memory DNN Computing

An Overview of Efficient Interconnection Networks for Deep Neural Network Accelerators

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