A Common Framework of NBTI Generation and Recovery in Plasma-Nitrided SiON p-MOSFETs

Deora, S.; Maheta, V.D.; Islam, Ahmad E.; Alam, Muhammad Ashraful; Mahapatra, S.

doi:10.1109/led.2009.2026436

Cited by 13 publications

(3 citation statements)

References 17 publications

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“…Most of the methods aim at applying a high stress bias for a specific period of time, and afterwards the state of the device is evaluated considering various ways. For instance stress-IV measurements, where IDVG sweeps are measured after a stress cycle has elapsed [ 17 ] have been used, but also hysteresis measurements [ 36 , 37 ], CV measurements [ 38 , 39 ], DLTS measurements [ 40 , 41 , 42 , 43 , 44 ] and on-the-fly methods [ 45 , 46 , 47 ] have been applied for assessment of the impact of charge trapping on the device performance. A common observation of the many measurement techniques used is that the

is observed to recover very fast, as soon as the stress bias is released [ 26 , 48 , 49 , 50 ].…”

Section: Measurement Techniques For Characterization Of Devicesmentioning

confidence: 99%

Reliability of Miniaturized Transistors from the Perspective of Single-Defects

Waltl

2020

Micromachines

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To analyze the reliability of semiconductor transistors, changes in the performance of the devices during operation are evaluated. A prominent effect altering the device behavior are the so called bias temperature instabilities (BTI), which emerge as a drift of the device threshold voltage over time. With ongoing miniaturization of the transistors towards a few tens of nanometer small devices the drift of the threshold voltage is observed to proceed in discrete steps. Quite interestingly, each of these steps correspond to charge capture or charge emission event of a certain defect in the atomic structure of the device. This observation paves the way for studying device reliability issues like BTI at the single-defect level. By considering single-defects the physical mechanism of charge trapping can be investigated very detailed. An in-depth understanding of the intricate charge trapping kinetics of the defects is essential for modeling of the device behavior and also for accurate estimation of the device lifetime amongst others. In this article the recent advancements in characterization, analysis and modeling of single-defects are reviewed.

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is observed to recover very fast, as soon as the stress bias is released [ 26 , 48 , 49 , 50 ].…”

Section: Measurement Techniques For Characterization Of Devicesmentioning

confidence: 99%

Reliability of Miniaturized Transistors from the Perspective of Single-Defects

Waltl

2020

Micromachines

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“…[6,19] During NBTI recovery phase, hole trapping in ∆N HT and ∆N OT can rapidly recover within several seconds. [6,20] A fraction of ∆N IT below the Fermi level may capture electrons, behaving as a fast recovery. On the other hand, the remaining broken bonds above the Femi level may be passivated by the back-diffused H 2 and H. The slow recovery of NBTI degradation is mainly contributed by the passivation of interface defects with back diffusion of H 2 .…”

Section: Nbti Recoverymentioning

confidence: 99%

Detailed study of NBTI characterization in 40-nm CMOS process using comprehensive models

Yan

Jiang

et al. 2017

Chinese Phys. B

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The impact of negative bias temperature instability (NBTI) can be ascribed to three mutually uncorrelated factors, including hole trapping by pre-existing traps (∆V HT ) in gate insulator, generated traps (∆V OT ) in bulk insulator, and interface trap generation (∆V IT ). In this paper, we have experimentally investigated the NBTI characteristic for a 40-nm complementary metal-oxide semiconductor (CMOS) process. The power-law time dependence, temperature activation, and field acceleration have also been explored based on the physical reaction-diffusion model. Moreover, the end-of-life of stressed device dependent on the variation of stress field and temperature have been evaluated. With the consideration of locking effect, the recovery characteristics have been modelled and discussed.

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“…We use R-D theory to model the interface defect dynamics, because it appears to consistently interpret a wide variety of NBTI experiments [1,[5][6][7][20][21][22][23][24]. In addition, many groups have used different variants of the R-D model in process qualification [1,6,25,26] and circuit design [26,27].…”

Section: Temporal Distribution Of Interface Defectmentioning

confidence: 99%

Analyzing the distribution of threshold voltage degradation in nanoscale transistors by using reaction-diffusion and percolation theory

Islam

Alam

2011

J Comput Electron

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Continued scaling of transistors into the nanoscale regime has led to large device-to-device variation in transistor characteristics. These variations reflect differences in substrate doping, channel length, interface and/or oxide defects, etc. among various transistors. In this paper, we develop a theory for the statistical distribution of threshold voltage degradation ( V T ) due to the Negative Bias Temperature Instability (NBTI). First, we model the time dynamics of interface defects within the Reaction-Diffusion (R-D) framework and calculate the statistics of interface defect using Markov Chain Monte-Carlo method. We show that the generation and annealing of interface defects are strongly correlated and that the statistics of interface defect at a given stress time (N IT @t STS ) follows a skew-normal distribution. Second, we explore the differential effect of the spatial distribution of interface defects in nanoscale transistors pre-populated with a discrete number of randomly placed substrate dopants. We model the effect of spatial distribution of defects using a percolative network and demonstrate that the distribution of threshold voltage degradation for a single additional interface defect, i.e., V T @ N IT = 1, is exponential, with a fraction of transistors having V T ∼ 0. Finally, we obtain the statis-Electronic supplementary material The online version of this article (tics of V T @t STS by convolving the statistics of N IT @t STS with that of V T @ N IT = 1. The resultant statistics of V T @t STS compares favorably with a broad range of experiments reported in the NBTI literature.

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A Common Framework of NBTI Generation and Recovery in Plasma-Nitrided SiON p-MOSFETs

Abstract: Abstract-Generation

Cited by 13 publications

References 17 publications

Reliability of Miniaturized Transistors from the Perspective of Single-Defects

Reliability of Miniaturized Transistors from the Perspective of Single-Defects

Detailed study of NBTI characterization in 40-nm CMOS process using comprehensive models

Analyzing the distribution of threshold voltage degradation in nanoscale transistors by using reaction-diffusion and percolation theory

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