A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0V cortex-M0 processor

Sun, Xun; Kim, Sung; Rahman, Fahim; Pamula, Venkata Rajesh; Li, Xi; John, Naveen; Sathe, Visvesh

doi:10.1109/isscc.2018.8310304

Cited by 10 publications

(3 citation statements)

References 4 publications

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“…Comparisons with other clocking stretching circuits [3], [4], [6] are shown in Table I. Some works provided bi-directional clocking to follow the supply droop [36]- [38], [42], [43]. Most of the current adaptive clocking circuits need one or more clock cycles for tuning, while ours has zero latency that it is able to stretch the clock cycle at the current cycle.…”

Section: B Measurement Of the Adaptive Clocking Circuitmentioning

confidence: 99%

“…Thus, they were able to provide a fast clocking for the supply droop mitigation [5], [6], [10]- [12], [39]- [41], by increasing clock cycle quickly to accommodate the worst case droop voltage. Besides these droop detection-based adaptive clock stretching circuits, there are adaptive frequency/voltage tracking circuits [36]- [38], which may either decrease or increase the frequency in response to the supply droop. Recently, unified voltage and frequency regulators were proposed to let the supply voltage recover from the droop besides tuning the frequency [42], [43].…”

Section: Introductionmentioning

confidence: 99%

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A Bi-Directional, Zero-Latency Adaptive Clocking Circuit in a 28-nm Wide AVFS System

Shan

Dai

Wan³

et al. 2020

IEEE J. Solid-State Circuits

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Resilient circuits based on in situ timing monitoring adaptive voltage-frequency scaling (AVFS) eliminate excess time margins caused by process, voltage, and temperature (PVT) variations but suffer from 50% throughput loss during error recovery when operating at a half frequency. We propose a bi-directional adaptive clocking circuit to provide fine frequency tuning with zero latency for AVFS system. It can either stretch the clock cycle when there are timing errors to ensure correct function or compress the cycle when there are excess timing margins. To support a wide frequency range, we generate multiple phase clocks based on two delay lines and select one appropriate phase clock to obtain a stretched output clock, where balanced clock paths are obtained by a time-to-digital converter and dynamic-OR gates. Applied to a wide-operating-range AVFS system of an SHA-256 accelerator with transition detector (TD) latches, the whole AVFS system is able to respond to errors in one clock cycle, with dynamic-OR gates collecting all the errors in half a cycle and adaptive clocking circuit stretching at the current cycle. Fabricated in 28-nm CMOS, chip measurement shows that it achieves 38.6%-69.4% power gains at near threshold while reducing throughput loss during error recovery.

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Section: B Measurement Of the Adaptive Clocking Circuitmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Bi-Directional, Zero-Latency Adaptive Clocking Circuit in a 28-nm Wide AVFS System

Shan

Dai

Wan³

et al. 2020

IEEE J. Solid-State Circuits

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“…As shown in Fig. 1, we have added the countermeasure hardware comprising (i) a machine-learning core capable of identifying CLKSCREW attack, titled a blacklist core (BL core) and (ii) timing error detection/prediction hardware such as tunable replica circuits (TRC) [14][15][16] and in-situ error detection and correction circuits (EDAC) [3,[11][12][13] for acquiring timing-error flags. The state-of-the-art EDAC techniques incur small silicon area overhead of <5% of a core area.…”

Section: Introductionmentioning

confidence: 99%

Blacklist Core

Zhang

Tang

Jiang

et al. 2018

Proceedings of the International Symposium on Low Power Electronics and Design

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Most modern computing devices make available fine-grained control of operating frequency and voltage for power management. These interfaces, as demonstrated by recent attacks, open up a new class of software fault injection attacks that compromise security on commodity devices. CLKSCREW, a recently-published attack that stretches the frequency of devices beyond their operational limits to induce faults, is one such attack. Statically and permanently limiting frequency and voltage modulation space, i.e., guard-banding, could mitigate such attacks but it incurs large performance degradation and long testing time. Instead, in this paper, we propose a run-time technique which dynamically blacklists unsafe operating performance points using a neural-net model. The model is first trained offline in the design time and then subsequently adjusted at run-time by inspecting a selected set of features such as power management control registers, timing-error signals, and core temperature. We designed the algorithm and hardware, titled a BlackList (BL) core, which is capable of detecting and mitigating such power management-based security attack at high accuracy. The BL core incurs a reasonably small amount of overhead in power, delay, and area. CCS CONCEPTS Security and privacy → Security in hardware → Hardware attacks and countermeasures → Side-channel analysis and countermeasures

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Conclusion

Reyserhove¹,

Dehaene²

2019

Efficient Design of Variation-Resilient Ultra-Low Energy Digital Processors

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A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0V cortex-M0 processor

Cited by 10 publications

References 4 publications

A Bi-Directional, Zero-Latency Adaptive Clocking Circuit in a 28-nm Wide AVFS System

A Bi-Directional, Zero-Latency Adaptive Clocking Circuit in a 28-nm Wide AVFS System

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