A Codesigned Integrated Photonic Electronic Neuron

Abstract

In the modern era of artificial intelligence, increasingly sophisticated artificial neural networks (ANNs) are implemented, which pose challenges in terms of execution speed and power consumption. To tackle this problem, recent research on reduced-precision ANNs opened the possibility to exploit analog hardware for neuromorphic acceleration. In this scenario, photonic-electronic engines are emerging as a short-medium term solution to exploit the high speed and inherent parallelism of optics for linear computations needed in ANN, while resorting to electronic circuitry for signal conditioning and memory storage.In this paper we introduce a precision-scalable integrated Photonic-Electronic Multiply-Accumulate Neuron (PEMAN). The proposed device relies on (i) an analog photonic engine to perform reduced-precision multiplications at high speed and low power, and (ii) an electronic front-end for accumulation and application of the nonlinear activation function by means of a nonlinear encoding in the analog-to-digital converter (ADC). The device has been numerically validated through cosimulations to perform multiply-accumulate operations (MAC). Simulations are based on the iSiPP50G SOI process for the photonic engine and a commercial 28 nm CMOS process for the electronic front-end. The PEMAN exhibits a multiplication accuracy of 6.1 ENOB up to 10 GMAC/s, while it can perform computations up to 56 GMAC/s with a reduced accuracy down to 2.1 ENOB. The device can trade off speed and power consumption with resolution, significantly outperforming its analog electronics counterparts both in terms of speed and power consumption.

Analysis of Integration Technologies for High-Speed Analog Neuromorphic Photonics

“…Nonetheless, the increased throughput and power efficiency brought by photonic accelerators come at a cost of some limitations in the neural network model design [24]. The number of inputs per neuron can vary from a few in all-optical approaches to several hundreds in electro-optic solutions [17]. Also, the depth of the architectures (i.e., the number of neural layers) and the implementable nonlinearities vary significantly [22].…”

“…Nonetheless, these approaches have a limited scalability imposed by the circuit complexity and the associated losses, which grow quadratically with the number of inputs [49]. In practical devices, the number of inputs per layer does not exceed ten, while projections on future devices are limited to 64 ports per chip [17].…”

“…To quantify the impact of different integration technologies on photonic neuromorphic devices, we have numerically evaluated the performance of a specific device: the Photonic Electronic Multiply-Accumulate Neuron (PEMAN) [17]. We have chosen this device as its processing core relies on two cascaded high-speed MZMs.…”

“…5 as a function of the speed. It has been evaluated considering 81 mW for the laser, 13 mW per EIC, 180 mW per highspeed DAC, and 400 mW per RF amplifier [17]. The RF amplifiers dissipate the highest share of power, which justifies the largest energy consumption for SOI devices.…”

“…To assess the impact of the integration platform on the performance of neuromorphic accelerator devices, in Sec. IV we report the numerical evaluation of the photonic-electronic multiply-accumulate neuron architecture (PEMAN [17]) and the 4-neuron Tensor-PEMAN [18], designed with the different technologies. Three key performance indicators have been assessed, namely (i) the bit resolution, (ii) the energy per operation, and (iii) the footprint efficiency (FE).…”