2007
DOI: 10.1109/jssc.2007.907195
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A CMOS Ultra-Wideband Receiver for Low Data-Rate Communication

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Cited by 64 publications
(27 citation statements)
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“…The power consumption is estimated assuming 0.18 µm CMOS technology [13]. The analog-to-digital-conversion (ADC) represents a bottle neck for obtaining a low-power UWB receive [14,15].…”
Section: Power Consumptionmentioning
confidence: 99%
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“…The power consumption is estimated assuming 0.18 µm CMOS technology [13]. The analog-to-digital-conversion (ADC) represents a bottle neck for obtaining a low-power UWB receive [14,15].…”
Section: Power Consumptionmentioning
confidence: 99%
“…One possible solution to reduce the power consumption is to place the ADC after the correlator, and hence the correlation is performed in the analog domain. This relaxes the ADC requirements, and consequently reduces the overall power consumption [13]. In particular, moving the correlation operation from the digital domain to the analog domain reduces the required sampling frequency from the Nyquist rate to the pulse repetition rate [13].…”
Section: Power Consumptionmentioning
confidence: 99%
See 1 more Smart Citation
“…Generally, ED receivers consume smaller amounts of power as compared to TR and fully digital architectures for the same design parameters. Figure 2 shows a comparison of the power consumption of four different receiver architectures based on the actual implementation parameters presented in [16,17]. As can be seen, ED receivers have the smallest power consumption as compared to TR and fully digital architectures.…”
Section: Sn R)mentioning
confidence: 99%
“…For a low data rate UWB link, typically a non-coherent receiver is implemented due to the simplicity in hardware architecture, low power consumption, and low energy efficiency [7][8][9]. However, non-coherent demodulation suffers bandwidth inefficiency and worse sensitivity.…”
Section: Introductionmentioning
confidence: 99%