A CMOS transconductor with 80-dB SFDR up to 10 MHz

Chilakapati, U.; Fiez, T.S.; Eshraghi, A.

doi:10.1109/4.987089

Cited by 57 publications

(16 citation statements)

References 15 publications

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“…In fact, the total area and power dissipation of the programmable integrator are comparable to those of other single opamp implementations found in literature for the same technology [12].…”

Section: Mos Current Divider-based Programmable Integratormentioning

confidence: 60%

Low-distortion 4th order programmable Butterworth filter

Sanz

Celma

Calvo

2007

Microelectronics Reliability

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Section: Mos Current Divider-based Programmable Integratormentioning

confidence: 60%

Low-distortion 4th order programmable Butterworth filter

Sanz

Celma

Calvo

2007

Microelectronics Reliability

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“…However, linearity is not greatly improved. Recently, some designs have been reported using a combination of two or more linearization techniques, like source degeneration, harmonic cancellation and adaptive bias schemes [12][13][14][15][16][17]. The performance obtained by these linearization techniques shows significant improvement from previous classical designs.…”

Section: Introductionmentioning

confidence: 99%

A tunable highly linear CMOS transconductor with 80 dB of SFDR

et al. 2009

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“…Approaches [18][19][20] provide higher SFDR. The proposed converter in [19] uses both the source resistors and output current differencing methods and can eliminate the third and fifth harmonics nearly completely.…”

Section: Circuit Designmentioning

confidence: 99%

“…In order to get a high spurious free dynamic range (SFDR) and also high signal-to-noise and distortion ratio (SINAD), the harmonics of the converter should be greatly eliminated in the design phase. Many voltage to current converters have been presented to date [14][15][16][17][18][19][20].…”

Section: Circuit Designmentioning

confidence: 99%

A 0.18-$\mu $m current-mode asynchronous sigma-delta modulator design

Kayaalti¹,

Cerid²,

Dündar³

2016

Turk J Elec Eng & Comp Sci

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Abstract:In this study a first-order asynchronous current-mode sigma-delta modulator has been designed and simulated.Asynchronous sigma-delta modulators eliminate the continuous time sigma-delta modulator's problem of signal-to-noise ratio degradation due to clock jitter by avoiding the use of sampling in the modulator loop. Moreover, they provide a higher signal-to-noise ratio even with low-order filters. Thus, considerably low power consumption can be achieved with fewer circuit components. The current mode enables designers to scale the circuits according to different supply voltages and operating currents. In this work, design steps for an asynchronous sigma-delta modulator have been given taking into account its ideal mathematical model. Novel current comparator architecture is proposed, which is used as a one bit-quantizer. Its working principles are explained. The comparator's operation is verified by the simulations in the asynchronous sigma-delta loop. Simulation results show that a satisfactory performance can be obtained with relatively simple designs, compared to ordinary synchronous continuous time sigma-delta modulators.

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A CMOS transconductor with 80-dB SFDR up to 10 MHz

Cited by 57 publications

References 15 publications

Low-distortion 4th order programmable Butterworth filter

Low-distortion 4th order programmable Butterworth filter

A tunable highly linear CMOS transconductor with 80 dB of SFDR

A 0.18-$\mu $m current-mode asynchronous sigma-delta modulator design

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