A CMOS square-law programmable floating resistor

A cellular neural network for solving a class of partial differential equations is presented. Each neural cell consists of a novel floating variable linear resistor, an amplifier, and a passive capacitor. The output of each cell is integrated with a Micro Electromechanical (MEMS) heater device that will be used for a thermal interface. The CMOS VLSI implementation of a nine cell network was designed and simulated. The results of this network are compared to the numerical solution of the partial differential equations.

show abstract

“…5. This range is larger than previous reported floating variable resistors [6], but still depends upon the threshold voltage.…”

Section: Fig 5 Simulation Results For the Floating Linear Variable contrasting

confidence: 53%

CMOS analog implementation of cellular neural network to solve partial differential equations with a microelectromechanical thermal interface

Rasmussen

Zaghloul

Proceedings of 40th Midwest Symposium on Circuits and Systems. Dedicated to the Memory of Professor Mac Van Valkenburg

View full text Add to dashboard Cite

show abstract

“…The first generation of MOS active resistors [1], [2] used MOS transistors working in the linear region, having the main disadvantages of an equivalent resistance inherently nonlinear and of obtaining distortion components that are complex functions on MOS technological parameters. A better design of CMOS active resistors is based on MOS transistors working in saturation [3], [4], [5]. Because of the quadratic characteristic of the MOS transistor, some linearisation techniques were developed in order to minimize the nonlinear terms from the current-voltage law of the active resistor.…”

Section: Introductionmentioning

confidence: 99%

Improved Linearity Active Resistors Using MOS and Floating-Gate MOS Transistors

Popa

2007

EUROCON 2007 - The International Conference on "Computer as a Tool"

View full text Add to dashboard Cite

A new linearity improvement technique for a CMOS active resistor will be presented, using an antiparallel connection of two quasi-identical active resistor structures, different biased and opposite excited. The second-order effects that affect the MOS transistor operation will be also taking into account, the proposed linearization method compensating also the linearity degradation imposed by these effects. In order to minimize the silicon area, an original method based on an optimal implementation of the current-controlled voltage generator will be presented. Additionally, the replacing of classical MOS transistors by FGMOS (Floating Gate MOS) active devices will further reduce the circuit complexity, and, thus, the area occupied on silicon, having the result of about two order of magnitude reducing area with respect to a classical resistor. The circuit estimated linearity error is under % 1 for an extended input range of mV 500 ± and for a small value of the supply voltage, V 3 V CC ± = . The proposed active resistor is designed for low-voltage low-power applications and it is implemented in m 35 0 µ . CMOS technology, the SPICE simulations confirming the theoretical estimated results.

show abstract

“…A better design of CMOS active resistors is based on MOS transistors working in saturation [3], [4]. Because of the quadratic characteristic of the MOS transistor, some linearisation techniques were developed in order to minimize the nonlinear terms from the current-voltage characteristic of the active resistor.…”

Section: Introductionmentioning

confidence: 99%

“…Usually, the resulting linearisation of the V I − characteristic is obtained by a first-order analysis. However, the second-order effects which affect the MOS transistor operation (mobility degradation, bulk effect and short-channel effect) limits the circuit linearity introducing odd and even-order distortions, as shown in [4].…”

Section: Introductionmentioning

confidence: 99%

Improved Linearity Active Resistor with Increased Frequency Response for VLSI Applications

Popa¹

2006

2006 IEEE International Conference on Automation, Quality and Testing, Robotics

View full text Add to dashboard Cite

An original active resistor circuit will be presented in this paper. The main advantages of the new proposed implementation are the improved linearity, the small area consumption and the improved frequency response. The frequency response of the circuit is very good as a result of operating all MOS transistors in the saturation region. The circuit is implemented in m 35 0 µ . CMOS technology, the SPICE simulation confirming the theoretical estimated results and showing a linearity error under a percent for an extended input range and a small value of the supply voltage. Index Terms-active resistor, linearity error, squaring and square-root circuits, complementary functions

show abstract

A CMOS square-law programmable floating resistor

Cited by 14 publications

References 3 publications

CMOS analog implementation of cellular neural network to solve partial differential equations with a microelectromechanical thermal interface

CMOS analog implementation of cellular neural network to solve partial differential equations with a microelectromechanical thermal interface

Improved Linearity Active Resistors Using MOS and Floating-Gate MOS Transistors

Improved Linearity Active Resistor with Increased Frequency Response for VLSI Applications

Contact Info

Product

Resources

About