A CMOS Power Amplifier using Ground Separation Technique

Abstract

This work presents an on-chip ground separation technique for power amplifiers. The ground separation technique is based on separating the grounds of the amplifier stages on the chip and thus any parasitic feedback paths are removed. Simulation and experimental results show that the technique makes the amplifier less sensitive to bondwire inductance, and consequently improves the stability and performance.A two-stage CMOS RF power amplifier for WCDMA mobile phones is designed using the proposed on chip ground separation technique. The power amplifier is fabricated in a 0.25,utm CMOS process. It has a measured 1-dB compression point between 1920MHz and 1980MHz of 21.3 ±0.5dBm with a maximum PAE of 24 c. The amplifier has sufficiently low ACLR for WCDMA (-33 dB) at an output power of 20 dBm.

Design of a one-watt level RF power amplifier for smartphones

“…A reported investigation [18] has shown that the substrate noise coupling between the power cells and transformers may affect the stability of RF power amplifiers, especially when the maximum output power of the RF power amplifier is high. To reduce the substrate noise coupling in the RF circuits, the substrate isolation techniques are reportedly employed.…”