A CMOS OTA with improved linearity based on current addition

Wu, P.; Schaumann, R.; Szczepański, S.

doi:10.1109/iscas.1990.112468

Cited by 15 publications

(9 citation statements)

References 8 publications

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“…The extension to MOS implementations operating in weak inversion is obvious and straightforward although scaling effects resulting from the altered coefficient of and errors arising from back-gate bias require consideration. However, the authors know of only two reported instances which di- rectly harness the square-law properties of MOS transistors for a similar purpose [23], [24] and propose the term "current-addition principle" when applying the concept to MOS process technology.…”

Section: Circuit Architecturementioning

confidence: 99%

“…For , the circuit reverts to the classical differential pair and will not be discussed further. However, for , the circuit is transformed into an unbalanced differential pair whose output current is given by [23] (2) where and are the drain currents of transistors and , respectively, and is the transconductance parameter; and are defined as (3) It becomes apparent from (2) that a differential output current of flows in an unbalanced differential pair when the applied differential input voltage is zero. In a balanced configuration, under the same operating conditions, the drain currents of the transistors which comprise the input pair are identical and, therefore, the differential output current is zero.…”

Section: A Linear Range and Transconductancementioning

confidence: 99%

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A Novel Pole–Zero Compensation Scheme Using Unbalanced Differential Pairs

Ryan

McCarthy

2004

IEEE Trans. Circuits Syst. I

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Abstract-The main problem in extending continuous-time filtering to higher frequencies is the sensitivity of high-frequency filters to analog integrator nonidealities such as finite dc gain and parasitic poles. The use of a cascode stage introduces internal nodes, and hence a nondominant pole, in the signal path. This has been overcome using a novel phase compensation scheme which does not require tuning of the compensating element, and is itself unaffected by tuning of the integrator's unity-gain frequency or quality factor. The scheme is based upon a MOS version of the "multi-tanh principle" where the linear range of a transconductor is divided between at least two unbalanced differential pairs operating in parallel. The common-source node of an unbalanced differential pair is not ac ground and the associated pole-zero pair may be harnessed to cancel the parasitic pole introduced by the cascode stage. The feasibility of the proposed design was evaluated with the fabrication of a test-chip on a 0.25 m 2.5 V standard digital CMOS process. Measurements confirm that the group delay response is flat ( 2%) over a five octave frequency range (3.5-112 MHz or 0.058-1.87 ).

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Section: Circuit Architecturementioning

confidence: 99%

Section: A Linear Range and Transconductancementioning

confidence: 99%

A Novel Pole–Zero Compensation Scheme Using Unbalanced Differential Pairs

Ryan

McCarthy

2004

IEEE Trans. Circuits Syst. I

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“…The transconductance count can be reduced by as much as a factor of two if fully differential transconductances are used22 which are readily available in integrated form. 19-21*33- 36 In addition, fully differential designs have the advantages of increased power supply rejection, dynamic range and linearity. Converting single-ended designs to differential form is trivial.…”

Section: Synthesis Techniquesmentioning

confidence: 99%

“…The two transconductance cells on the left and right (OTA3, OTA4) were added as part of our continuing effort in transconductance cell development. 36 The experimental output from the 25 MHz lowpass filter is shown in Figure 9. 53 Note that the two filters are largely identical in layout except for the size of the capacitors.…”

Section: -0s +mentioning

confidence: 99%

Automation of the ic layout of continuous‐time transconductance‐capacitor filters

Daasch

Wedlake

Schaumann

et al. 1992

Circuit Theory & Apps

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SUMMARYTo exploit the increased circuit density available in current technologies for continuous-time (c-t) systems, it is proposed to extend the range of analogue design automation to the larger c-t subsystems, specifically filters, commonly found in communications, mass storage devices and other interfaces to real-world signals. The synthesis is based on LC ladder simulation using only transconductances and grounded capacitors (TGC). The method retains many of the characteristics of digital design automation and therefore allows a direct mapping of these techniques. The TGC approach is shown to require a minimum of component types which are ideally suited to integration in MOS, bipolar or GaAs technologies. A simple example for the automation of c-t filter designs as well as results of CMOS c-t filters are included to demonstrate the viability of this approach. Related and equally important areas addressed are tuning, compensation for parasitics and scaling.

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“…When the output currents of pairs 1, 2, and 3 are added as shown in figure 3, the total output current is lout = Iol + Io2 + lo3 (9) The reason for using the connection for current addition shown in figure 3, rather than that in [24] and [25], is to make the currents in M7 and M8 symmetrical in order to facilitate the design of a differential output lOOu 80u"…”

Section: The Practical Designmentioning

confidence: 99%

Design considerations for CMOS and GaAs OTAs: Frequency response, linearity, tuning, and common-mode feedback

Schaumann

1991

Analog Integr Circ Sig Process

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High-performance operational transconductance amplifiers (OTAs) are important in the design of highfrequency analog transconductance-C (gin-C) filters. Critical design considerations for OTAs are frequency response, linearity, tuning, output impedance, power supply rejection (PSR), and common-mode rejection (CMR). In CMOS technology, satisfactory OTA design techniques are available, except that the linear input range often is relatively small and the frequency response of the OTA is limited by the intrinsic speed of transistors. In this paper, a new approach is developed to increase the linear input range, and a trade-off between linearity and input range is discussed. A CMOS OTA with less than +0.4% linearity error over a very large input range is given as a design example. To achieve a very high frequency response, l~m depletion-mode GaAs MESFETs with high intrinsic speed are used to replace MOSFETs. Simple ac compensation, a new technique for output impedance enhancement, and a new tuning method for OTAs with all N-channel devices are used to design a GaAs OTA with very small parasitics and f-3JB = 7 GHz. To improve PSR and CMR, fully balanced structures are used for the OTAs. Design considerations for the interaction of the operation of common-mode feedback (CMF) and tuning are discussed, and improved CMF circuits are proposed. Using the GaAs OTA and considering the frequency limitations imposed by parasitics, the design of a high order ladder filter with 300MHz cutoff frequency is presented as an application.

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A CMOS OTA with improved linearity based on current addition

Cited by 15 publications

References 8 publications

A Novel Pole–Zero Compensation Scheme Using Unbalanced Differential Pairs

A Novel Pole–Zero Compensation Scheme Using Unbalanced Differential Pairs

Automation of the ic layout of continuous‐time transconductance‐capacitor filters

Design considerations for CMOS and GaAs OTAs: Frequency response, linearity, tuning, and common-mode feedback

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