A CMOS Imaging Diversity Receiver Chip with a Flip-Chip Integrated Detector Array for Optical Wireless Links

Abstract

⎯ An optical receiver circuit incorporating a novel current-mode, channel selection and combination circuit architecture is presented. Optical measurements at 310Mb/s are demonstrated on the CMOS receiver chip flip-chip bonded to a custom detector array.

On the Design of Low-Power Front-End Receiver Circuits for Broadband Optical Free-Space Links

“…As light enters the receiver at different angles, one or more detectors are illuminated. The diversity combiner is designed to monitor the received optical power level, apply variable signal weights, and select individual channels for arbitrary combination of signals to enhance clock and data recovery [5]. Significant power savings can be achieved by on-chip estimation of the signal-to-noise ratio (SNR) at each channel and powering down channels that are weakly illuminated.…”

“…A scalable, lowpower implementation of the diversity combiner circuit proposed in Figure 1 is presented in Figure 3. Channel signal level estimation, weighting, selection, and combination are implemented using on-chip analog signal processing at the front-end [5]. The front-end preamplifier output drives a variable gain transconductance stage producing output current signals steered by externally controlled switches to a current bus-bar (summing junction).…”

A CMOS imaging diversity receiver for gigabit free-space optical MIMO

“…1. Compared to the EGC diversity receiver realized in [12], this architecture avoids current-voltage-current conversion and directly amplifies and combines current signals from multiple channels, which reduces circuit complexity, lowers power consumption, and improves noise performance. In a real system, imaging optics are employed to map the received LOS optical signal to a subset of detectors depending on the transmitter illumination pattern and angle of arrival.…”

An area-efficient maximum-ratio-combining diversity receiver in 90 nm CMOS for free-space optical links

“…Level shifting transistors M4 and M9 enable greater flexibility in d.c. coupling of subsequent amplifier stages, resulting in smaller chip footprint due to the absence of large a.c. coupling capacitors. Furthermore, the diversity receiver topology increases in scalability enabling on-chip integration of arbitrary numbers of receiving channels [17].…”