A CMOS continuous-time G/sub m/-C filter for PRML read channel applications at 150 Mb/s and beyond

Mehr, I.; Welland, D.R.

doi:10.1109/4.563671

Cited by 85 publications

(38 citation statements)

References 32 publications

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“…The most general form of the low-pass filter transfer function is given by (18) The values for the natural frequency and of the individual biquads were chosen to satisfy a 0.05 equiripple-phase characteristic [32], where (19) The biquad order was dictated by the process of minimizing transient and dc gains from the input to the integrating nodes. Specifically, the biquads are ordered according to increasing natural frequency and quality factor [10], [33]. Referring once again to Fig.…”

Section: Resultsmentioning

confidence: 99%

“…A slightly negative output conductance will not cause filter instability, however, because of negative feedback, loops inherently present in the biquadratic loop . Regardless, the most popular choice is the inclusion of a cascode stage (simple [9], [10], active [11], [12], folded [13], [14], telescopic [15], [16]) or a cascaded output stage such as the -op-amp [17]- [21] to improve the integrator dc gain, and attempt to cancel the associated parasitics directly.…”

Section: Introductionmentioning

confidence: 99%

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A Novel Pole–Zero Compensation Scheme Using Unbalanced Differential Pairs

Ryan

McCarthy

2004

IEEE Trans. Circuits Syst. I

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Abstract-The main problem in extending continuous-time filtering to higher frequencies is the sensitivity of high-frequency filters to analog integrator nonidealities such as finite dc gain and parasitic poles. The use of a cascode stage introduces internal nodes, and hence a nondominant pole, in the signal path. This has been overcome using a novel phase compensation scheme which does not require tuning of the compensating element, and is itself unaffected by tuning of the integrator's unity-gain frequency or quality factor. The scheme is based upon a MOS version of the "multi-tanh principle" where the linear range of a transconductor is divided between at least two unbalanced differential pairs operating in parallel. The common-source node of an unbalanced differential pair is not ac ground and the associated pole-zero pair may be harnessed to cancel the parasitic pole introduced by the cascode stage. The feasibility of the proposed design was evaluated with the fabrication of a test-chip on a 0.25 m 2.5 V standard digital CMOS process. Measurements confirm that the group delay response is flat ( 2%) over a five octave frequency range (3.5-112 MHz or 0.058-1.87 ).

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Novel Pole–Zero Compensation Scheme Using Unbalanced Differential Pairs

Ryan

McCarthy

2004

IEEE Trans. Circuits Syst. I

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“…Several high performance OTA architectures have been proposed. The folded-cascode, telescopic architecture [6] increases the output impedance and therefore provides high gain and good noise rejection. However, they are not suitable for high frequency linear phase filter design because the non-dominant pole degrades the performance of the filter [7].…”

Section: Ota Designmentioning

confidence: 99%

“…Different architectures can result in significant performance differences for implementation of a given filter response. Design methods for high-order active filters including the cascade, LC ladder simulation, and multiple loop feedback (MLF) are well established [1][2][3][4][5][6][7][8]. The main drawback of the cascade realization is high sensitivity to filter parameter variations and component tolerances.…”

Section: Introductionmentioning

confidence: 99%

A CMOS 650 MHz seventh-order current-mode 0.05° equiripple linear phase filter

Zhu

Sun

Moritz

2007

2007 50th Midwest Symposium on Circuits and Systems

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Read/write channels for hard disk drives (HDD) require high-frequency continuous time filters (CTF) [1][2][3][4][5]. A 650 MHz current-mode seventh-order 0.05° equiripple linear phase low-pass filter for computer hard disk read/write channels with data rates up to 1Gbit/s is presented in this paper. It is implemented in CMOS using a leap-frog multiple loop feedback structure. The operational transconductance amplifier (OTA) used is based on a differential pair and uses source degeneration to achieve linearization and tuning. Simulated using a standard 0.18µm CMOS process, the dynamic range at 1% THD of the filter is 48dB, cut-off frequency can be tuned from 590MHz to 690MHz, group delay ripple is about 5%, and power consumption is 370mW from supply voltage of 2.5V.

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“…Voltage at node X can be considered constant due to the very low resistance at node X provided by the FVF, which is given by r x =1/(g m6 ⋅g m7 ⋅r 6 ), where g m6 and g m7 are the small-signal transconductance gains of M 6 and M 7 , respectively; and r 6 is the small-signal output resistance of M 6 . This circuit solution based on the FVF scheme leads to a compact implementation.…”

Section: Principle Of Operationmentioning

confidence: 99%

Low-Voltage Tunable Pseudo-Differential Transconductor with High Linearity

Galán¹,

Carrasco²,

Pennisi³

et al. 2009

ETRI J

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A novel tunable transconductor is presented. Input transistors operate in the triode region to achieve programmable voltage-to-current conversion. These transistors are kept in the triode region by a novel negative feedback loop which features simplicity, low voltage requirements, and high output resistance. A linearity analysis is carried out which demonstrates how the proposed transconductance tuning scheme leads to high linearity in a wide transconductance range. Measurement results for a 0.5 μm CMOS implementation of the transconductor show a transconductance tuning range of more than a decade (15 μA/V to 165 μA/V) and a total harmonic distortion of −67 dB at 1 MHz for an input of 1 V pp and a supply voltage of 1.8 V.

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A CMOS continuous-time G/sub m/-C filter for PRML read channel applications at 150 Mb/s and beyond

Cited by 85 publications

References 32 publications

A Novel Pole–Zero Compensation Scheme Using Unbalanced Differential Pairs

A Novel Pole–Zero Compensation Scheme Using Unbalanced Differential Pairs

A CMOS 650 MHz seventh-order current-mode 0.05° equiripple linear phase filter

Low-Voltage Tunable Pseudo-Differential Transconductor with High Linearity

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A CMOS continuous-time G/sub m/-C filter for PRML read channel applications at 150 Mb/s and beyond

Cited by 85 publications

References 32 publications

A Novel Pole–Zero Compensation Scheme Using Unbalanced Differential Pairs

A Novel Pole–Zero Compensation Scheme Using Unbalanced Differential Pairs

A CMOS 650 MHz seventh-order current-mode 0.05&#x00B0; equiripple linear phase filter

Low-Voltage Tunable Pseudo-Differential Transconductor with High Linearity

Contact Info

Product

Resources

About

A CMOS 650 MHz seventh-order current-mode 0.05° equiripple linear phase filter