A CMOS clock-frame regeneration chip with ECL-compatible input/output [for SONET]

Chang, Zu-yao; Delarbre, A.; Schelfhout, K.; Vanzieleghem, E.; Haspeslagh, J.

doi:10.1109/edac.1993.386470

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A CMOS clock-frame regeneration chip with ECL-compatible input/output [for SONET]

Cited by 2 publications

References 4 publications

Pulsewidth control loop in high-speed CMOS clock buffers

Pulsewidth control loop in high-speed CMOS clock buffers

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