A CMOS adaptive continuous-time forward equalizer, LPF, and RAM-DFE for magnetic recording

Brown, J. E.; Hurst, P.J.; Rothenberg, B.C.; Lewis, S.H.

doi:10.1109/4.743762

Cited by 28 publications

(3 citation statements)

References 29 publications

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“…Non-linear effects on postcursor ISI can be canceled by detecting the sequence of the previous symbols, and subtracting the corresponding RAM-stored value (for a particular sequence) from the signal at the input of the slicer. Brown et al [11] also proposed a complete RAM-DFE chip with 11.2mm 2 operating at 80Mb/s and dissipating 630mW using a first order continuous-time forward equalizer and a 4-tap FIR backward equalizer. MDFE was proposed by Kenney et al [12] as a quasi-optimum implementation of a maximum-likelihood sequence detector for run-length-limited (1,7) encoded data.…”

Section: B Decision Feedback Equalization Read Channelsmentioning

confidence: 99%

Equalization in hard disk drive read channels

Garrido

Cercas

2014

2014 21st International Conference on Telecommunications (ICT)

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This paper presents a comprehensive non-exhaustive comparative study of hard disk drive read-channel equalization techniques used in the readback process of magnetically stored information. The main read channel architectures: partial-response maximum likelihood (PRML) and decision feedback equalization (DFE) based systems, are compared in power consumption, layout area, data signalling rate and data density. This work focuses on the key component of the read channel, presenting a continuous-time analog solution for the pulse-slimming equalizer capable of reducing power consumption and die area by a factor of ten, whilst showing equivalent response to a FIR filter implementation.

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Section: B Decision Feedback Equalization Read Channelsmentioning

confidence: 99%

Equalization in hard disk drive read channels

Garrido

Cercas

2014

2014 21st International Conference on Telecommunications (ICT)

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“…The first term would suggest that the use of cascode output stages is mandatory. However, some implementations have avoided their use because they introduce additional nodes, and hence parasitics, in the signal path [2]- [5]. Instead, they rely on automatic tuning circuitry to control the quality factor.…”

Section: Introductionmentioning

confidence: 99%

“…One approach harnesses the output impedance of a saturated transistor, which is proportional to its bias current and inversely proportional to its length, to tune without sacrificing the frequency response or linearity [6]- [8]. Another technique cancels the finite output conductance of a transconductor using a negative resistance load, thereby increasing its dc gain which can, in theory, be made infinite [2], [3], [5]. A slightly negative output conductance will not cause filter instability, however, because of negative feedback, loops inherently present in the biquadratic loop .…”

Section: Introductionmentioning

confidence: 99%

A Novel Pole–Zero Compensation Scheme Using Unbalanced Differential Pairs

Ryan

McCarthy

2004

IEEE Trans. Circuits Syst. I

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Abstract-The main problem in extending continuous-time filtering to higher frequencies is the sensitivity of high-frequency filters to analog integrator nonidealities such as finite dc gain and parasitic poles. The use of a cascode stage introduces internal nodes, and hence a nondominant pole, in the signal path. This has been overcome using a novel phase compensation scheme which does not require tuning of the compensating element, and is itself unaffected by tuning of the integrator's unity-gain frequency or quality factor. The scheme is based upon a MOS version of the "multi-tanh principle" where the linear range of a transconductor is divided between at least two unbalanced differential pairs operating in parallel. The common-source node of an unbalanced differential pair is not ac ground and the associated pole-zero pair may be harnessed to cancel the parasitic pole introduced by the cascode stage. The feasibility of the proposed design was evaluated with the fabrication of a test-chip on a 0.25 m 2.5 V standard digital CMOS process. Measurements confirm that the group delay response is flat ( 2%) over a five octave frequency range (3.5-112 MHz or 0.058-1.87 ).

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Practical Design and Applications of Current-mode Systems

Mohan¹

2003

Current-Mode VLSI Analog Filters

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A CMOS adaptive continuous-time forward equalizer, LPF, and RAM-DFE for magnetic recording

Cited by 28 publications

References 29 publications

Equalization in hard disk drive read channels

Equalization in hard disk drive read channels

A Novel Pole–Zero Compensation Scheme Using Unbalanced Differential Pairs

Practical Design and Applications of Current-mode Systems

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