A CMOS 4.6ppm/°C curvature-compensated bandgap voltage reference

Liu, Shubin; Zhu, Zhangming; Gu, Huaxi; Liu, Minjie; Liu, Lianxi; Yang, Yintang

doi:10.1587/elex.9.1617

Cited by 3 publications

(1 citation statement)

References 7 publications

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“…The conventional Bandgap VR using bipolar transistors usually requires high supply voltage and consumes around µW power [1,2]. To overcome those disadvantages, the state-of-the-art VRs gradually substitute subthreshold MOSFETs for bipolar transistors [3,5,6,9]. As a result, the supply voltage can reduce to under 1 V and power consumption may be lower to several nW or even pW [4,7,8,10].…”

Section: Introductionmentioning

confidence: 99%

A 0.85 V, 4.9 ppm/°C inherent temperature compensated voltage reference with −82 dB PSRR

Zhou

Shi

Yuan

et al. 2018

IEICE Electron. Express

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A novel high PSRR and inherent temperature compensated CMOS voltage reference is present. A resistorless self-biased current source (RLSBCS) is proposed, formed by a gate-source voltage division (GSVD) structure, to achieve a temperature compensated proportional thresholdvoltage difference. Meanwhile, a self-cascode structure is adopted to further cancel the residual negative temperature dependence of proposed thresholdvoltage difference. Besides, feedback and self-bias techniques are introduced to enhance PSRR. The temperature coefficient is 4.9 ppm/°C in the temperature range of −25°C to 75°C and PSRR at DC is −82 dB with a power consumption of 9.8 nW.

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Section: Introductionmentioning

confidence: 99%

A 0.85 V, 4.9 ppm/°C inherent temperature compensated voltage reference with −82 dB PSRR

Zhou

Shi

Yuan

et al. 2018

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

Sub-1 V, 5.5 ppm/°C, High PSRR all CMOS Bandgap Voltage Reference

Khan

2018

IETE Journal of Research

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An Improved Bandgap Reference with Curvature-Compensated and High Power Supply Rejection

Liu

2016

J CIRCUIT SYST COMP

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This paper presents a bandgap reference (BGR) with the characteristics of curvature-compensation and high power supply rejection ratio (PSRR). To achieve a better performance, the base current of BJT is injected to a small segment of resistor string to flatten the temperature variation, and a pre-regulator of the power supply is implemented to improve the PSRR. The circuits, designed in 0.18[Formula: see text][Formula: see text]m BCD technology, exhibit an average voltage of 1.212[Formula: see text]V with temperature coefficient of 2.0[Formula: see text]ppm/[Formula: see text] in the range from [Formula: see text] to 110[Formula: see text] at typical condition, and a power supply rejection ratio of [Formula: see text][Formula: see text]dB at low frequency. After 4-bit trimming, Monte Carlo simulation results show that the proposed design gets an accuracy of 0.29%, with a variation of [Formula: see text][Formula: see text]mV. The active design area is 160[Formula: see text][Formula: see text]m, and the power supply current is about 8.2[Formula: see text][Formula: see text]A.

show abstract

A CMOS 4.6ppm/°C curvature-compensated bandgap voltage reference

Cited by 3 publications

References 7 publications

A 0.85 V, 4.9 ppm/°C inherent temperature compensated voltage reference with −82 dB PSRR

A 0.85 V, 4.9 ppm/°C inherent temperature compensated voltage reference with −82 dB PSRR

Sub-1 V, 5.5 ppm/°C, High PSRR all CMOS Bandgap Voltage Reference

An Improved Bandgap Reference with Curvature-Compensated and High Power Supply Rejection

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