A CMOS 135–150 GHz 0.4 dBm EIRP transmitter with 5.1dB P1dB extension using IF envelope feed-forward gain compensation

Abstract

A CMOS D-band 135-150 GHz transmitter is presented with integrated digital control and on-chip antenna. The proposed transmitter employs an IF feed-forward compensation scheme which improves the soft gain compression of the power amplifier by 5.1dB to provide an overall more linear AM-AM profile allowing reduced power back-off for modulation schemes with a high peak-to-average ratio. The proposed D-band transmitter consumes 255mW and occupies 2000 x 1500 um of silicon area. The proposed transmitter delivers a 0.4 dBm EIRP and a saturated power on chip of 13.2 dBm. The transmitter has a peak PAE of 8.2% with power delivered to the antenna and a peak PAE of 0.4% when considering radiated power.

CMOS mm-wave transceiver techniques beyond 50 GHz

“…Also in [6], an on-chip DAC and DDS provided signal generation so that input power could be swept and the large signal response captured by the power sensor providing the output compression curve (gain vs. power out) for linearity optimization of P1 dB. Re-using a variant of the transmitter chip from [3] (with photograph shown in Fig. 6a), we measured the radiated output power (EIRP) of 20 chips (procedure described in [3]) when the DAC control codes were at mid-scale of 127/256, which represents the optimum simulated value.…”

“…Re-using a variant of the transmitter chip from [3] (with photograph shown in Fig. 6a), we measured the radiated output power (EIRP) of 20 chips (procedure described in [3]) when the DAC control codes were at mid-scale of 127/256, which represents the optimum simulated value. The EIRP measurement histogram is shown in Fig 6b. The power sensor is used in conjunction with a PC and a data acquisition card to perform a binary code search and optimize the front-end settings.…”

“…The EIRP measurement histogram is shown in Fig 6b. The power sensor is used in conjunction with a PC and a data acquisition card to perform a binary code search and optimize the front-end settings. In this experiment the LO is generated from an onchip synthesizer (design detailed in [3]) which is phase-locked to a crystal reference, so the LO frequency does not vary from chip to chip relative to the PA center frequency. Results of the binary-search optimization are shown for the 20 chips in Fig.…”

“…Design of RF front-ends at mm-wave carriers (100 GHz) and beyond is a relatively new topic with most emphasis placed on the circuit design aspects. One major challenge of mm-wave front-ends operating at frequencies beyond 100 GHz is that the stage gain for power amplifiers is quite low [1,2,3], typically only 3-6 dB of gain per stage. This low available gain makes the front-end extremely sensitive to the effects of process variation as a small change in the CMOS device parameters may drastically reduce the front-end performance.…”

“…The design was fabricated on two different wafer runs spaced 6 months apart and 10 chips were selected from each run for a total of 20 chips. Using a setup similar to the one discussed in [3], the center frequency and output power of each chip was measured at the same supply and bias conditions for each chip. 2 and 3 plot the output frequency and power measured from the 20 chips respectively.…”