10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003
DOI: 10.1109/icecs.2003.1301667
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A clock jitter insensitive multibit DAC architecture for high-performance low-power continuous-time ΣΔ modulators

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“…Nonetheless, it took several years then to see promising techniques in the literature: the first technique was published in [136] and extensively reviewed in [31,33,[199][200][201], while it was previously patented in [202]. Here, an exponentially decaying feedback pulse is realized with a switched-capacitor-resistor (SCR) arrangement, which intends to imitate the sloping feedback pulse-form of switched-capacitor implemented, DT modulators in the feedback path of continuous-time architectures.…”
Section: Reduction Of Clock Jitter Influence Using Shaped Feedback Wamentioning
confidence: 99%
“…Nonetheless, it took several years then to see promising techniques in the literature: the first technique was published in [136] and extensively reviewed in [31,33,[199][200][201], while it was previously patented in [202]. Here, an exponentially decaying feedback pulse is realized with a switched-capacitor-resistor (SCR) arrangement, which intends to imitate the sloping feedback pulse-form of switched-capacitor implemented, DT modulators in the feedback path of continuous-time architectures.…”
Section: Reduction Of Clock Jitter Influence Using Shaped Feedback Wamentioning
confidence: 99%