A class of code compression schemes for reducing power consumption in embedded microprocessor systems

Benini, Luca; Menichelli, Francesco; Olivieri, Mauro

doi:10.1109/tc.2004.1268405

Cited by 22 publications

(13 citation statements)

References 19 publications

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“…This results in code size reduction by 30 to 40%, but reduces performance by 15 to 20% (Bonny and Henkel, 2008) and also requires a decoder and de-compressor inside the processor to support both ISAs. The other drawback of this approach (Benini et al, 2004) is the performance penalty caused by lack of several instructions in the dense instruction set. This approach customizes the existing RISC instruction set architecture with narrow instructions supporting fewer operations, smaller operand fields and fewer registers.…”

Section: Related Workmentioning

confidence: 99%

A Case for Hybrid Instruction Encoding for Reducing Code Size in Embedded System-on-Chips Based on Risc Processor Cores

Bakthavatsalam¹

2014

Journal of Computer Science

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Embedded computing differs from general purpose computing in several aspects. In most embedded systems, size, cost and power consumption are more important than performance. In embedded System-onChips (SoC), memory is a scarce resource and it poses constraints on chip space, cost and power consumption. Whereas fixed instruction length feature of RISC architecture simplifies instruction decoding and pipeline implementation, its undesirable side effect is code size increase caused by large number of unused bits. Code size reduction minimizes memory size, chip space and power consumption all of which are significant for low power portable embedded systems. Though code size reduction has drawn the attention of architects and developers, the solutions currently used are more of cure than of prevention. Considering the huge number of embedded applications, there is a need for a dedicated processor optimized for low power and portable embedded systems. In the study, we propose a variation of Hybrid Instruction Encoding (HIE) for the embedded processors. Our scheme uses fixed number of multiple instruction lengths with provision for hybrid sizes for the offset and the immediate fields thereby reducing the number of unused bits. We simulated the HIE for the MIPS32 processors and measured code sizes of various embedded applications of MiBench and MediaBench benchmarks using an offline tool developed newly. We noticed up to 27% code reduction for large and medium sized embedded applications respectively. This results in reduction of on-chip memory capacity up to 1 mega bytes that is very significant for SoC based embedded applications. Considering the large market share of embedded systems, it is worth investing in a new architecture and development of dedicated HIE-RISC processor cores for portable embedded systems based on SoCs.

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Section: Related Workmentioning

confidence: 99%

A Case for Hybrid Instruction Encoding for Reducing Code Size in Embedded System-on-Chips Based on Risc Processor Cores

Bakthavatsalam¹

2014

Journal of Computer Science

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“…The decompression unit is placed between the processor core and memory due to which there is an increase in chip space [4]. Wolfe and Chanin [5] were the first to apply code compression to embedded systems.…”

Section: Code Compressionmentioning

confidence: 99%

Code Size Reduction in Embedded Systems with Redesigned ISA for RISC Processors

B¹,

Mehata²

2013

IJCA

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Reducing the size of a program is a major goal in modern embedded systems. Large code occupies more space in the Chip and also causes higher power consumption because of increased memory traffic. In this paper, a revised architecture is proposed for embedded processors by replacing the Loadstore Architecture with Register-Memory Architecture for selected instructions. Analysis of RISC object code for Embedded Applications, using an offline tool developed by the authors, establishes the scope for a new class of processor exclusively for embedded applications. We have used this tool to simulate Register-Memory Architecture for MIPS processor. Based on the results, MIPS processor's instruction set is enhanced with 12 new instructions of Register-Memory Architecture. Experimental results for MiBench Benchmark programs with Register-Memory Architecture Simulation reveal that code size reduction up to 22% can be achieved with modified MIPS Architecture. This is also applicable for microMIPS processor that claims 35% code space saving with 16-bit instructions, thus offering a total of over 55% code space reduction compared to MIPS32 Architecture, for embedded systems. Equivalent memory reduction achieved is very significant for Embedded Systems built using SOCs. Processor design modifications, required at microarchitecture level, are also identified. Other additional features that can be combined with Register-Memory Architecture for an efficient embedded processor are identified.

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“…[6,9,26,31,59], and save storage space [2,44]. Over the last decade, compression has been implemented at various levels of the memory hierarchy and proved to be a successful method of saving energy.…”

Section: Saving Energy Using Compressionmentioning

confidence: 99%

Energy and performance evaluation of lossless file data compression on server systems

Kothiyal

Tarasov

Sehgal

et al. 2009

Proceedings of SYSTOR 2009: The Israeli Experimental Systems Conference

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of the Thesis Energy and Performance Evaluation of Lossless File Data Compression on Computer Systems by Rachita Kothiyal Master of Science in Computer ScienceStony Brook University 2009Data compression has been claimed to be an attractive solution to save energy consumption in high-end servers and data centers. However, there has not been a study to explore this. In this thesis, we present a comprehensive evaluation of energy consumption for various file compression techniques implemented in software. We apply various compression tools available on Linux to a variety of data files, and we try them on server, workstation and laptop class systems. We compare their energy and performance results against raw reads and writes. Our results reveal that software based data compression cannot be considered as a universal solution to reduce energy consumption. Various factors like the type of the data file, the compression tool being used, the read-to-write ratio of the workload, and the hardware configuration of the system impact the efficacy of this technique. We found that in some cases, compression can save as much as 33% energy and improve performance by 37.85%. However, in other cases we found that compression can increase energy consumption 7 times and deteriorate performance 4 fold.iii To my parents and my sisters, Ruchi and Rachna.

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A class of code compression schemes for reducing power consumption in embedded microprocessor systems

Cited by 22 publications

References 19 publications

A Case for Hybrid Instruction Encoding for Reducing Code Size in Embedded System-on-Chips Based on Risc Processor Cores

A Case for Hybrid Instruction Encoding for Reducing Code Size in Embedded System-on-Chips Based on Risc Processor Cores

Code Size Reduction in Embedded Systems with Redesigned ISA for RISC Processors

Energy and performance evaluation of lossless file data compression on server systems

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