2007
DOI: 10.1002/mop.23106
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A class‐E CMOS RF power amplifier with cascaded class‐D driver amplifier

Abstract: A 800‐MHz power amplifier is designed using a 0.18‐μm RF CMOS process. The voltage‐combining method is used for power combining. A transmission line transformer on a printed circuit board (PCB) is designed as a power combiner. For the switching mode power amplifier, a cascaded class‐D driver amplifier is proposed using a feedback resistor and a DC‐blocking capacitor. The power amplifier has an output power of 32.9 dBm and a power‐added efficiency of 60.25%. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol … Show more

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Cited by 6 publications
(3 citation statements)
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“…If the designed power amplifier is in switching mode, a driver stage supports the transistors of the power stage to operate as switch while the power stage generates high output power. One well‐known driver stage, due to its small size, is the Class‐D type . Figure (a) shows simple schematics of the Class‐D type driver stage.…”
Section: Typical Class‐d Type Driver Stagementioning
confidence: 99%
“…If the designed power amplifier is in switching mode, a driver stage supports the transistors of the power stage to operate as switch while the power stage generates high output power. One well‐known driver stage, due to its small size, is the Class‐D type . Figure (a) shows simple schematics of the Class‐D type driver stage.…”
Section: Typical Class‐d Type Driver Stagementioning
confidence: 99%
“…The driver stage is designed to be of class‐D type. The feedback resistor between the input and the output of the driver stage is used to moderate the process variations . The supply voltage of the driver stage is identical to that of the power stage.…”
Section: Proposed Structure Of the Power Stagementioning
confidence: 99%
“…1. These feedback resistors can provide stable DC bias voltage to the class-D amplifiers and they can reduce DC current consumption compared with a bias technique with dividing resistors [3]. The driver stage needs to be optimized at 5 GHz in order to obtain required power gain with minimum power consumption.…”
Section: Circuit Designmentioning
confidence: 99%