A circuit technique to compensate PVT variations in a 28 nm CMOS cascode power amplifier

Abstract

This paper presents a method to compensate CMOS process-, voltage-, and temperature (PVT) variations in a linear two-stage RF power amplifier (PA). The proposed circuit technique mitigates bias point fluctuations caused by non-controllable uncertainties like wafer-dependent electron mobility, increasing die temperature due to substrate self-heating, or supply voltage deviations. A scaled PA replica cascode circuit and a controlled current mirror form a feedback loop which stabilizes the PA operation point over a wide range of PVT variations. As demonstrated by simulations and verified by measurements, the PA operating conditions have been stabilized over a temperature range of 90 • C and more than 0.5 V supply change. The proposed biasing scheme has been implemented using a 28 nm standard CMOS process. The PA is able to deliver more than one Watt of RF output power at a peak power-added efficiency (PAE) of 33 % at 1.8 GHz center frequency operation.