A Circuit for Robustness Enhancement of the Subthreshold SRAM Bitcell in 65nm Technology

Abstract

This paper describes a circuit which can enhance the robustness of the subthreshold 6T SRAM bitcell. The proposed circuit can dynamically adjust the body voltages of the PMOS transistors in order to enhance the robustness of the subthreshold 6T SRAM bitcell by detecting the variation of the threshold voltage. The simulation results under 300mV in 65nm technology demonstrate that the mean values of the read and hold static noise margin (SNM) of the subthreshold 6T SRAM bitcell have been improved by 18% and 0.7%, respectively, meanwhile the standard values of the read and hold SNM have improved by 82% and 29.4%, respectively, by adopting the proposed circuit. Moreover, the proposed circuit functions well in a wide range of supply voltage from 0.2V to 0.5V.