A chip set architecture for programmable real-time MPEG2 video encoder

Matsumura, Toshiro; Segawa, H.; Matsuura, Shiro; Hanami, A.; Yamaoka, H.; Streitenberger, R.; Nakagawa, Shinichi; Ishihara, Kengo; Kasezawa, Tadashi; Ajioka, Yoshiaki; Maeda, Atsushi; Yoshimoto, Masahiko

doi:10.1109/cicc.1995.518210

Cited by 19 publications

(6 citation statements)

References 6 publications

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“…Due to large frame sizes, the frame memory has the highest capacitance in the system, dominating its energy dissipation. Although there has been a significant progress in low-power memory design, the frame memory alone still accounts over 35% of the total energy [1]. Therefore, it must be optimized for low energy consumption as much as possible.…”

Section: A Motivationmentioning

confidence: 99%

Reducing energy dissipation of frame memory by adaptive bit-width compression

Moshnyaga

2002

IEEE Trans. Circuits Syst. Video Technol.

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In this paper, we propose a new architectural technique to reduce energy dissipation of frame memory through adaptive bitwith compression. Unlike related approaches, the technique utilizes the fixed order of memory accesses and data correlation of video sequences by dynamically adjusting the memory bitwidth to the number of bits changed per pixel. Instead of treating data bits independently, we group the most significant bits together, activating the corresponding group of bit lines adaptively to data variation. The approach is not restricted to specific bit patterns, nor does it depend on the storage phase. It works equally well on read and write accesses, as well as during precharging. Simulations show that in using this method, we can reduce the total energy consumption of frame memory by 20% without affecting the picture quality. The implementation scheme is simple yet compact.

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Section: A Motivationmentioning

confidence: 99%

Reducing energy dissipation of frame memory by adaptive bit-width compression

Moshnyaga

2002

IEEE Trans. Circuits Syst. Video Technol.

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“…The performance and required hardware amount of a motion estimation algorithm largely depend on its block-matching criterion. The SAD [3] is widely used in most of the conventional motion estimation algorithms because of its efficiency and simplicity, but its hardware cost is rather high for VLSI implementation if the search range is large [7]. Therefore, several block-matching criteria have been proposed to reduce this hardware cost, which are defined as follows.…”

Section: B Block-matching Criterionmentioning

confidence: 99%

“…Regarded as the optimum solution for obtaining a high compression ratio [6], this method suffers from a tremendous hardware cost. It becomes impractical for hardware implementation if the search range is large [7]. Therefore, many fast algorithms have been proposed [8]- [15] to reduce this hardware cost.…”

Section: Introductionmentioning

confidence: 99%

New motion estimation algorithm using adaptively quantized low bit-resolution image and its VLSI architecture for MPEG2 video encoding

Lee

Kim

Chae

1998

IEEE Trans. Circuits Syst. Video Technol.

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This paper describes a new motion estimation algorithm that is suitable for hardware implementation and substantially reduces the hardware cost by using a low bit-resolution image in the block matching. In the low bit-resolution image generation, adaptive quantization is employed to reduce the bit resolution of the pixel values, which is better than simple truncation of the least significant bits in preserving the dynamic range of the pixel values. The proposed algorithm consists of two search steps: in the low-resolution search, a set of candidate motion vectors is determined, and in the full-resolution search, the motion vector is found from these candidate motion vectors. The hardware cost of the proposed algorithm is 1/17 times of the full search algorithm, while its peak signal-to-noise ratio is better than that of the 4 : 1 alternate subsampling for the search range of 632 2 632: A VLSI architecture of the proposed algorithm is also described, which can concurrently perform two prediction modes of the MPEG2 video standard with the search range of (032.0,032.0)-(+31.5,+31.5). We fabricated a MPEG2 motion estimator with a 0.5-m triple-metal CMOS technology. The VLSI chip includes 110 K gates of random logic and 90 K bits of SRAM in a die size of 11.5 mm 2 12.5 mm. The full functionality of the fabricated chip was confirmed with an MPEG2 encoder chip.

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“…With the success of DSS deployment, MPEGZ technology is gaining momentum in the digital media world. Some MPEG2 video encoder chip sets [3,4] have been introduced recently and show that the development is complex and costly. Although the MPEG2 operational characteristics are well suited for some applications, it only satisfies others in limited fashion [SI .…”

Section: Introductionmentioning

confidence: 99%