A case study on MPEG4 decoder design with SystemBuilder

Shibata, Seiya; Honda, Shinya; Tomiyama, Hiroyuki; Takada, Hiroaki

doi:10.1109/vdat.2009.5158168

Cited by 3 publications

(2 citation statements)

References 4 publications

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“…We designed an MPEG4 decoder system with SystemBuilder. Based on the MPEG4 decoder developed in the past 20) , we improved performance of the design using the process profiler and the memory profiler (Fig. 9).…”

Section: Mpeg4 Decoder System Designmentioning

confidence: 99%

Efficient Design Space Exploration at System Level with Automatic Profiler Instrumentation

Shibata

Ando

Honda

et al. 2010

IPSJ Transactions on System LSI Design Methodology

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As the complexity of embedded systems grows, design space exploration at a system level plays a more important role than before. In the system-level design, system designers start from describing functionalities of the system as processes and channels, and then decide mapping of them to various Processing Elements (PEs) including processors and dedicated hardware modules. A mapping decision is evaluated by simulation or FPGA-based prototyping. Designers iterate mapping and evaluation until all design requirements are met. We have developed two profilers, a process profiler and a memory profiler, for FPGA-based performance analysis of design candidates. The process profiler records a trace of process activations, while the memory profiler records a trace of channel accesses. According to mapping of processes to PEs, the profilers are automatically configured and instrumented into FPGA-based system prototypes by a system-level design tool that we have developed. Designers therefore need to manually modify neither the system description nor the profilers upon each change of process mapping. In order to demonstrate the effectiveness of our profilers, two case studies are conducted where the profiles are used for design space exploration of AES encryption and MPEG4 decoding systems.

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Section: Mpeg4 Decoder System Designmentioning

confidence: 99%

Efficient Design Space Exploration at System Level with Automatic Profiler Instrumentation

Shibata

Ando

Honda

et al. 2010

IPSJ Transactions on System LSI Design Methodology

Self Cite

View full text Add to dashboard Cite

show abstract

“…Based on the MPEG4 decoder developed in the past [13], we improved performance of the design using the process profiler and the memory profiler.…”

Section: A Case Study: Mpeg4 Decoder System Designmentioning

confidence: 99%

Automatic instrumentation of profilers for FPGA-based design space exploration

Shibata

Ando

Honda

et al. 2009

2009 International Conference on Field-Programmable Technology

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In the system-level design of MPSoCs (MultiProcessor System-on-a-Chips), system designers start from describing functionalities of the system as processes and channels, and then decide mapping of them to various Processing Elements (PEs) including CPUs and dedicated hardware modules. A mapping decision is evaluated by simulation or FPGA-based prototyping. Designers iterate mapping and evaluation until all design requirements are met. We have developed two profilers, a process profiler and a memory profiler, for FPGA-based performance analysis of design candidates. The process profiler records a trace of process activations, while the memory profiler records a trace of channel accesses. According to mapping of processes to PEs, the profilers are automatically configured and instrumented into FPGA-based system prototypes by a systemlevel design tool that we have developed. Designers therefore need to manually modify neither the system description nor the profilers upon each change of process mapping. In order to demonstrate the effectiveness of our profilers, a case study on MPEG4 decoder design was conducted.

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Dependencies data flow graph based approach for speeding-up application

Debbi

2016

2016 International Conference on Industrial Informatics and Computer Systems (CIICS)

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A case study on MPEG4 decoder design with SystemBuilder

Cited by 3 publications

References 4 publications

Efficient Design Space Exploration at System Level with Automatic Profiler Instrumentation

Efficient Design Space Exploration at System Level with Automatic Profiler Instrumentation

Automatic instrumentation of profilers for FPGA-based design space exploration

Dependencies data flow graph based approach for speeding-up application

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