A case study on exploration of last-level cache for energy reduction in DDR3 DRAM

Min, Su Myat; Javaid, Haris; Ignjatović, Aleksandar; Parameswaran, Sri

doi:10.1109/meco.2013.6601372

Cited by 1 publication

(4 citation statements)

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“…We chose SoCs, their estimation methodologies and component models from existing works [23,24,25] because we were able to reproduce those works.…”

Section: Case Studiesmentioning

confidence: 99%

“…The authors of [23] used a SoC similar to Figure 1(a), and considered multiple L2 cache configurations resulting from three parameters: cache size, line size and associativity. They proposed a statistical model to estimate the total energy saving of L2 cache and DRAM memory when L2 cache is changed and lowpower mode is used for DRAM during its idle periods.…”

Section: Case Studiesmentioning

confidence: 99%

“…[ # se l f -co n f i g s. # d e si g n p o i n t s]Figure 6: Application of FALCON to (a) uniprocessor SoC[23] (b) multiprocessor pipeline SoC[24] (c) multiprocessor mesh NoC SoC[25].for all the 330 cache configurations. The authors of[23] manually determined the number and order of model executions, where as FALCON automatically executed these models in the correct order with minimal executions to gather the energy savings of all the design points, reducing designer's effort.…”

mentioning

confidence: 99%

“…The authors of[23] manually determined the number and order of model executions, where as FALCON automatically executed these models in the correct order with minimal executions to gather the energy savings of all the design points, reducing designer's effort. Note that the accuracy of FALCON is similar to[23] since we used their component models without any modifications.Case Study 2: Multiprocessor Pipeline SoC. The authors of…”

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confidence: 99%

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Falcon

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Yachide

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et al. 2014

Proceedings of the 51st Annual Design Automation Conference

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In this paper, we focus on systematic and efficient computation (accurate value or an estimate) of metrics such as performance, power, energy, etc. of a component-based parameterized system-on-chip (SoC). Traditionally, given models of SoC components (such as cycle-accurate simulator of a processor, trace-based simulator of a cache/memory), a designer manually determines an execution schedule of these models (such as execute processor simulator, followed by cache/memory simulator) to combine/propagate their individual results for computation of a SoC metric.To reduce designer's effort, we propose FALCON, a framework where the execution schedule of component models is generated automatically, and a minimal number of model executions is used to compute values of a SoC metric for the given component models and design space (resulting from component parameter values). FALCON is semi-automated, is applicable to a wide range of SoC platforms with ease, and works with existing design space exploration algorithms. In three case studies (uniprocessor system, multiprocessor pipeline system and multiprocessor mesh network-on-chip system), FALCON reduced designer's effort (measured in minutes) by at least two orders of magnitude.

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“…We chose SoCs, their estimation methodologies and component models from existing works [23,24,25] because we were able to reproduce those works.…”

Section: Case Studiesmentioning

confidence: 99%

Section: Case Studiesmentioning

confidence: 99%