A case study in porting a production scientific supercomputing application to a reconfigurable computer

Kindratenko, Volodymyr; Pointer, W. David

doi:10.1109/fccm.2006.5

Cited by 58 publications

(45 citation statements)

References 2 publications

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“…An example of an MD system, NAMD was also successfully accelerated with FPGAs. 8 Another example is the ProtoMol framework, which was designed especially for computational experimentation and so has well-defined partitions among computations. 9 We have found that the acceleratable kernel not only comprises more than 90 percent of execution time with ProtoMol, but the modularity enables straightforward integration of an FPGA accelerator.…”

Section: Methods 4: Living With Amdahl's Lawmentioning

confidence: 99%

Achieving High Performance with FPGA-Based Computing

et al. 2007

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Numerous application areas, including bioinformatics and computational biology, demand increasing amounts of processing capability. In many cases, the computation cores and data types are suited to field-programmable gate arrays. The challenge is identifying the design techniques that can extract high performance potential from the FPGA fabric.Accelerating high-performance computing (HPC) applications with field-programmable gate arrays (FPGAs) can potentially deliver enormous performance. A thousand-fold parallelism is possible, especially for low-precision computations. Moreover, since control is configured into the logic itself, overhead instructions-such as array indexing and loop computationsneed not be emulated, and every operation can deliver payload.At the same time, using FPGAs presents significant challenges 1 including low operating frequency-an FPGA clocks at one-tenth that of a high-end microprocessor. Another is simply Amdahl's law: To achieve the speedup factors required for user acceptance of a new technology (preferably 50 times), 2 at least 98 percent of the target application must lend itself to substantial acceleration. As a result, HPC/FPGA application performance is unusually sensitive to the implementation's quality.The problem of achieving significant speedups on a new architecture without expending exorbitant development effort, and while retaining flexibility, portability, and maintainability, is a classic one. In this case, accelerating HPC applications with FPGAs is similar to that of porting uniprocessor applications to massively parallel processors, with two key distinctions:• FPGAs are far more different from uniprocessors than MPPs are from uniprocessors, and• the process of parallelizing code for MPPs, while challenging, is still better understood and supported than porting codes to FPGAs.Lawrence Snyder stated the three basic parameters for the MPP portability problem. 3 First, a parallel solution using P processors can improve the best sequential solution by a factor of P, at most. Second, HPC problems tend to have third-or fourth-order complexity, and so parallel computation, while essential, offers only modest benefits. Third, "the whole force of parallelism must be transferred to the problem, not converted to 'heat' of implementational overhead."Researchers have addressed the portability problem periodically over the past 30 years, with well-known approaches involving language design, optimizing compilers, emulation, software engineering tools and methods, and function and application libraries. It is generally agreed that compromises are required: Either restrict the variety of architectures or scope of application, or bound expectations of performance or ease of implementation.

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Section: Methods 4: Living With Amdahl's Lawmentioning

confidence: 99%

Achieving High Performance with FPGA-Based Computing

et al. 2007

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“…The GRAPE PGR system [28] is one of the recent efforts in developing a design framework, but currently it does not support optimizations in the algorithmarchitecture design space. Also, some early efforts made towards modeling molecular dynamics using SRC Computers in [29], [30], involve specialized language and manual intervention in many key steps such as extracting data dependency information (used in timing analysis). In contrast, TANOR provides a fully automated framework for different N-body interaction problems.…”

Section: Scientific Application: N-body Problemsmentioning

confidence: 99%

An Automated Framework for Accelerating Numerical Algorithms on Reconfigurable Platforms Using Algorithmic/Architectural Optimization

Kim

Deng

Mangalagiri

et al. 2009

IEEE Trans. Comput.

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Abstract-This paper describes TANOR, an automated framework for designing hardware accelerators for numerical computation on reconfigurable platforms. Applications utilizing numerical algorithms on large-size data sets require high-throughput computation platforms. The focus is on N-body interaction problems which have a wide range of applications spanning from astrophysics to molecular dynamics. The TANOR design flow starts with a MATLAB description of a particular interaction function, its parameters, and certain architectural constraints specified through a graphical user interface. Subsequently, TANOR automatically generates a configuration bitstream for a target FPGA along with associated drivers and control software necessary to direct the application from a host PC. Architectural exploration is facilitated through support for fully custom fixed-point and floating point representations in addition to standard number representations such as single precision floating point. Moreover, TANOR enables joint exploration of algorithmic and architectural variations in realizing efficient hardware accelerators. TANOR's capabilities have been demonstrated for three different N-body interaction applications: the calculation of gravitational potential in astrophysics, the diffusion or convolution with Gaussian kernel common in image processing applications, and the force calculation with vector-valued kernel function in molecular dynamics simulation. Experimental results show that TANOR-generated hardware accelerators achieve lower resource utilization without compromising numerical accuracy, in comparison to other existing custom accelerators.

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“…The three most notable examples are a molecular dynamics application [Kindratenko and Pointer 2006;Scrofano et al 2006], a full CG solver [Morris et al 2006], and a traffic simulation engine [Tripp et al 2005]. None of these efforts have considered requirements for future systems attempting to leverage FPGAs.…”

Section: Related Workmentioning

confidence: 99%

“…While there are exceptions (notably molecular dynamics (MD) [Kindratenko and Pointer 2006;Scrofano et al 2006]), these applications tend to be hundreds of thousands of lines of code without a small section that dominates execution time. This led researchers to begin by focusing on kernel operations that are used in HPC and can be provided through a standard library interface.…”

Section: Introductionmentioning

confidence: 99%

Architectures and APIs: Assessing Requirements for Delivering FPGA Performance to Applications

Underwood¹,

Hemmert²,

Ulmer³

2006

ACM/IEEE SC 2006 Conference (SC'06)

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Reconfigurable computing leveraging field programmable gate arrays (FPGAs) is one of many accelerator technologies that are being investigated for application to high performance computing (HPC). Like most accelerators, FPGAs are very efficient at both dense matrix multiplication and FFT computations, but two important aspects of how to deliver that performance to applications have received too little attention. First, the standard API for important compute kernels hides parallelism from the system. Second, the issue of system architecture is virtually never addressed. This paper explores both issues and their implications for applications. We find that high bandwidth, low latency connectivity can be important, but the right API can be even more important.

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A case study in porting a production scientific supercomputing application to a reconfigurable computer

Cited by 58 publications

References 2 publications

Achieving High Performance with FPGA-Based Computing

Achieving High Performance with FPGA-Based Computing

An Automated Framework for Accelerating Numerical Algorithms on Reconfigurable Platforms Using Algorithmic/Architectural Optimization

Architectures and APIs: Assessing Requirements for Delivering FPGA Performance to Applications

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