A Case Study for NoC-Based Homogeneous MPSoC Architectures

Abstract

The many-core design paradigm requires flexible and modular hardware and software components to provide the required scalability to next-generation on-chip multiprocessor architectures. A multidisciplinary approach is necessary to consider all the interactions between the different components of the design. In this paper, a complete design methodology that tackles at once the aspects of system level modeling, hardware architecture, and programming model has been successfully used for the implementation of a multiprocessor network-on-chip (NoC)-based system, the NoCRay graphic accelerator. The design, based on 16 processors, after prototyping with field-programmable gate array (FPGA), has been laid out in 90-nm technology. Post-layout results show very low power, area, as well as 500 MHz of clock frequency. Results show that an array of small and simple processors outperform a single high-end general purpose processor. Index Terms-Multiprocessor systems-on-chip (MP-SoC), network-onchip (NoC).

A quantitative evaluation of a Network on Chip design flow for multi-core consumer multimedia applications

“…In addition to FPGAs, complete NoC-based SoC ASICs are presented in [7,17,72] together with a post-layout evaluation. However, neither of the works evaluate the scalability and instead focus on a single design point.…”

“…However, neither of the works evaluate the scalability and instead focus on a single design point. Moreover, rather than considering the IPs given, the works in [2,22,43,52,72] customise the entire system to fit with the NoC, e.g. by modifying the IPs [43] or adding NoC-specific instructions [72].…”

“…Moreover, rather than considering the IPs given, the works in [2,22,43,52,72] customise the entire system to fit with the NoC, e.g. by modifying the IPs [43] or adding NoC-specific instructions [72]. In an industrial context this is often not possible and the interconnect has to accommodate a wide range of IP interfaces [29].…”

“…NoCs address the physical scalability by splitting the interconnect into multiple segments with relaxed timing requirements [16,64] and offer architectural scalability through a structured and modular architecture [6]. It is thus possible to implement a network that scales with the number of IPs in the design [43,72]. NoCs also offer guaranteed services, i.e.…”

Design of a Wideband Antenna for Wireless Network-On-Chip in Multimedia Applications

“…This is the case of both homogeneous and heterogeneous MPSoCs [5,6]. In Homogeneous MPSoCs [7][8][9][10], all the interconnected tiles are of the same type; for example, eight MagicDSP tiles, each integrating an ARM TM core plus a VLIW (Very Long Instruction Word) processor, are interconnected through a NoC in [8]. Instead, multiple ARM Cortex cores are integrated on-chip in [10] to implement cloud sever-on-chip solutions.…”