A case for wireless 3D NoCs for CMPs

Matsutani, Hiroki; Bogdan, Paul; Mărculescu, Radu; Take, Yasuhiro; Sasaki, Daisuke; Zhang, Hao; Koibuchi, Michihiro; Kuroda, Tadahiro; Amano, Hideharu

doi:10.1109/aspdac.2013.6509553

Cited by 40 publications

(21 citation statements)

References 13 publications

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“…Matsutani et al [6] and Take et al [25] mention that card-style computer components (i.e., chips) are inserted to a microcartridge that provides only power and clock pins to the chips. They assume these chips communicate each other wirelessly without going through the cartridge that would limit the bandwidth due to pin-count limitation.…”

Section: B Inductive-coupling Thruchip Interfacementioning

confidence: 99%

Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces

Kagami

Matsutani

Koibuchi

et al. 2016

IEEE Trans. VLSI Syst.

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Wireless 3-D network-on-chips (NoCs) with inductive-coupling ThruChip interfaces provide a large degree of flexibility for customizing the number of arbitrary chips in a package after chips have been fabricated. To simplify the vertical communication interfaces, static time division multiple access (TDMA) is used for the vertical broadcast buses, while arbitrary or customized topologies can be used for the intrachip network. This paper proposes two techniques to break through the simple static TDMA-based vertical buses while maintaining a simple communication interface. The first technique is headfirst sliding (HS) routing to reduce the waiting time for acquiring the communication time-slot. HS routing selects the best vertical bus based on the current time, taking advantage of static TDMA. The second technique extends carrier sense multiple access with collision detection (CSMA/CD) for vertical broadcast buses. We introduce a packet collision detection technique for inductive-coupling buses and propose two retransmission strategies to reduce the waiting time for packet retransmissions caused by collisions. Network simulation results show that HS routing reduces the communication latency by 39.1% compared with the conventional static TDMA bus-based 3-D NoC that uses the shortest path routing. The proposed CSMA/CD bus also improves the latency by 52.5% and throughput by 34.1%. The full-system simulation results show that HS routing and the proposed CSMA/CD technique reduce the application execution time accordingly while maintaining the average flit transfer energy overhead modest. IndexTerms-3-D integration, inductive-coupling, interconnection network, network-on-chip (NoC), ThruChip interface (TCI).

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Section: B Inductive-coupling Thruchip Interfacementioning

confidence: 99%

Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces

Kagami

Matsutani

Koibuchi

et al. 2016

IEEE Trans. VLSI Syst.

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“…The HiRy-based routing method with two VCs is compared with the conventional up*/down* routing [19] with the best combination of two spanning trees [26]. Each of the two methods is utilized as the escape paths of Duato's protocol [16] that can achieve minimal adaptive routing with nonminimal deadlock-free escape paths.…”

Section: Applying To Duato's Protocolmentioning

confidence: 99%

A Generalized Theory Based on the Turn Model for Deadlock-Free Irregular Networks

Kawano¹,

Yasudo

Matsutani³

et al. 2020

IEICE Trans. Inf. & Syst.

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Recently proposed irregular networks can reduce the latency for both on-chip and off-chip systems with a large number of computing nodes and thus can improve the performance of parallel applications. However, these networks usually suffer from deadlocks in routing packets when using a naive minimal path routing algorithm. To solve this problem, we focus attention on a lately proposed theory that generalizes the turn model to maintain the network performance with deadlock-freedom. The theorems remain a challenge of applying themselves to arbitrary topologies including fully irregular networks. In this paper, we advance the theorems to completely general ones. Moreover, we provide a feasible implementation of a deadlock-free routing method based on our advanced theorem. Experimental results show that the routing method based on our proposed theorem can improve the network throughput by up to 138 % compared to a conventional deterministic minimal routing method. Moreover, when utilized as the escape path in Duato's protocol, it can improve the throughput by up to 26.3 % compared with the conventional up*/down* routing.

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“…Three emerging interconnects (three-dimensional (3D), photonic, and RF/wireless NoCs [3][4] [5]) were introduced to address the long range multi-hop communication bottleneck. Inductive/capacitive-coupled 3D integration technology [6] is another alternative to wireless interconnects but it produces electromagnetic interference through unwanted coupling. The photonic NoC achieves a higher bandwidth than Wireless Network-on-Chip (WiNoC).…”

Section: Introductionmentioning

confidence: 99%

Broadcast Mechanism Based on Hybrid Wireless/Wired NoC for Efficient Barrier Synchronization in Parallel Computing

Mondal

Chatterjee

Cataldo

et al. 2020

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)

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Parallel computing is essential to achieve the manycore architecture performance potential, since it utilizes the parallel nature provided by the hardware for its computing. These applications will inevitably have to synchronize its parallel execution: for instance, broadcast operations for barrier synchronization. Conventional network-on-chip architectures for broadcast operations limit the performance as the synchronization is affected significantly due to the critical path communications that increase the network latency and degrade the performance drastically. A Wireless network-on-chip offers a promising solution to reduce the critical path communication bottlenecks of such conventional architectures by providing hardware broadcast support. We propose efficient barrier synchronization support using hybrid wireless/wired NoC to reduce the cost of broadcast operations. The proposed architecture reduces the barrier synchronization cost up to 42.79% regarding network latency and saves up to 42.65% communication energy consumption for a subset of applications from the PARSEC benchmark.

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A case for wireless 3D NoCs for CMPs

Cited by 40 publications

References 13 publications

Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces

Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces

A Generalized Theory Based on the Turn Model for Deadlock-Free Irregular Networks

Broadcast Mechanism Based on Hybrid Wireless/Wired NoC for Efficient Barrier Synchronization in Parallel Computing

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