A Carrier Recovery Loop for Cognitive Radio Applications

Abstract

From the issue entitled "Special Issue on Embedded Signal Processing Circuits and Systems for Cognitive Radio-Based Wireless Communication Devices"International audienceThe increasing demands for wireless communication especially in consumer electronics applications, result in substantially and continuously increasing reliability and Quality of Service (QoS) requirements. This trend creates a need to introduce intelligent functionalities in the wireless devices, which leads to the concept of Cognitive Radio (CR) technology. In some CR applications such as Dynamic Spectrum Access (DSA), the CR terminal should be able to modify its transmission parameters in order to communicate with an efficient utilization of the spectrum resource. In such a case, the CR terminal would be capable of reconfiguring itself with minimum supplementary information to achieve best performance. In this paper we propose a blind carrier recovery loop with respect to the modulation scheme suited to CR applications. Unlike conventional solutions which use a separate modulation identification device before performing carrier recovery, the introduced loop employs a hierarchical symbol decision to achieve phase lock, and then the S-curve and the variance of a Decision-Directed phase error detector are used to extract an information about the modulation scheme of the incoming signal. After the phase lock with the hierarchical decision the constellation used in the received signal is detected and then the true decisions are used to drive the recovery loop. Results obtained with different digital linear modulations (8-PSK, 16-QAM, 16-APSK, 64-QAM) indicate that the introduced loop is capable of achieving a real-time modulation scheme detection as well as keeping phase lock in case of adaptive modulation scheme transmissions

Blind I/Q Imbalance Compensation for M-QAM Optical Coherent Systems Based on Pseudo-Rotation

“…The value of the phase offset α can be estimated using a second order Digital Phase Locked Loop (DPLL) [12].…”