A CAM-Free Exascalable HPC Router for Low-Energy Communications

Concatto, Caroline; Pascual, José Antonio; Navaridas, Javier; Lant, Joshua; Attwood, Andrew; Luján, Mikel; Goodacre, John

doi:10.1007/978-3-319-77610-1_8

Cited by 7 publications

(9 citation statements)

References 21 publications

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“…While several other solutions [14], [15], [16], allow for this sort of dataflow processing, they typically only support point-to-point links between the FPGAs, severely limiting the topologies which can be created [16], which in turn severely limits scalability. Combined with our switch design [8], our solution can exploit modern HPC topologies such as Jellyfish, Dragonfly and Fat-Trees.…”

Section: Our Solutionmentioning

confidence: 99%

“…Our solution is the first (to our knowledge) to maintain both tight-coupling with system memory, and fully decoupled networking capability. We analyze our lightweight NIC which leverages a custom network protocol based on a simple geographic addressing scheme [8]; supporting HW prim- itives for both shared memory and RDMA operations, and including a custom reliable transport layer. Our system-level transport layer enables modern, low-diameter topologies to be built, rather than using simple point-to-point connections as most of the literature uses (limiting scalability).…”

Section: Introductionmentioning

confidence: 99%

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Enabling Standalone FPGA Computing

Lant

Navaridas

Attwood³

et al. 2019

2019 IEEE Symposium on High-Performance Interconnects (HOTI)

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One of the key obstacles in the advancement of largescale distributed FPGA platforms is the ability of the accelerator to act autonomously from the CPU, whilst maintaining tight coupling to system memory. This work details our efforts in decoupling the networking capabilities of the FPGA from CPU resources using a custom transport layer and network protocol. We highlight the reasons that previous solutions are insufficient for the requirements of HPC, and we show the performance benefits of offloading our transport into the FPGA fabric. Our results show promising throughput and latency benefits, and show competitive Flops being achievable for network dependent computing in a distributed environment.

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Section: Our Solutionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Enabling Standalone FPGA Computing

Lant

Navaridas

Attwood³

et al. 2019

2019 IEEE Symposium on High-Performance Interconnects (HOTI)

Self Cite

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“…In case this perfect allocation is not possible, it will try to reduce the distance between the node and the NVM containing the data in order to reduce the utilization of network resources. Regarding the communication infrastructure, we are building our own multi‐tier, custom‐made FPGA‐based interconnection within ExaNeSt and, indeed, in Manchester, we are in charge of the Top‐of‐Rack (ToR) routers . Given the high flexibility provided by FPGA devices, we are exploring the adequacy of a range of mechanisms to be incorporated into our design, out of which, traffic prioritization is one of the most promising and so, studied here.…”

Section: The Exanest Architecturementioning

confidence: 99%

“…The aforementioned allocation strategies are implemented at the software‐level. However, as we are also developing a router within ExaNeSt, we also want to evaluate to what extent the allocation of network resources to flows impact the performance of the applications when mixed traffic is present. For this reason, we also evaluate a number of policies to assign priorities to the traffic, which translate into bandwidth reservation.…”

Section: Introductionmentioning

confidence: 99%

On the effects of allocation strategies for exascale computing systems with distributed storage and unified interconnects

Pascual

Lant

Concatto

et al. 2018

Concurrency and Computation

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The convergence between computing-and data-centric workloads and platforms is imposing new challenges on how to best use the resources of modern computing systems. In this paper, we investigate alternatives for the storage subsystem of a novel exascale-capable system with special emphasis on how allocation strategies would affect the overall performance. We consider several aspects of data-aware allocation such as the effect of spatial and temporal locality, the affinity of data to storage sources, and the network-level traffic prioritization for different types of flows.In our experimental set-up, temporal locality can have a substantial effect on application runtime (up to a 10% reduction), whereas spatial locality can be even more significant (up to one order of magnitude faster with perfect locality). The use of structured access patterns to the data and the allocation of bandwidth at the network level can also have a significant impact (up to 20% and 17% reduction of runtime, respectively). These results suggest that scheduling policies exposing data-locality information can be essential for the appropriate utilization of future large-scale systems. Finally, we found that the distributed storage system we are implementing can outperform traditional SAN architectures, even with a much smaller (in terms of I/O servers) back-end. KEYWORDSinter-processor communications, near-data computing, resource allocation, scheduling, storage traffic INTRODUCTIONTraditionally, supercomputers have been used to execute large computing-intensive parallel applications such as scientific codes. However, nowadays, new types of data-oriented applications are becoming increasingly popular. In contrast with traditional high performance computing (HPC) codes, they have to process massive amounts of scientific or business-oriented data and, hence, impose completely different needs to the computing systems.Indeed, new hardware and software are being developed to suit these necessities. One of these systems is our novel, custom-made architecture,ExaNeSt. 1 We are working on the design and construction of a prototype capable of reaching Exascale computation using tens of millions of interconnected low-power-consumption ARM cores. 2 To support such kind of data-intensive applications, we are leveraging a unified, low-latency Interconnection Network (hereafter, IN) and a fully distributed storage subsystem, BeeGFS, with the data spread across the nodes in local non-volatile storage devices 3 (NVM). This greatly contrasts with traditional supercomputers and datacenters that rely on Storage Area Networks (SAN) to access the data with separate networks for I/O, system management, and inter-processor communications (IPC).A fully distributed file system allows for near-data computation, reducing the great overheads of moving data from the centralized storage to the compute nodes. 4 A single, consolidated IN offers enormous power-savings when compared with multi-network designs. While a unified IN does, indeed, allow us to cope with power and co...

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“…The ExaNeSt interconnect is a multi‐tier interconnect, which can be divided into two distinct parts. The lower tiers, which are physically fixed by means of boards and backplanes, and the higher tiers, which are fully reconfigurable using custom‐made FPGA‐based routers. This flexibility allows to build any network topology, ie, direct, indirect, or hybrid, or even the use of standard off‐the‐shelf commodity switches.…”

Section: Introductionmentioning

confidence: 99%

Modeling and analysis of the performance of exascale photonic networks

Duro

Pascual

Petit

et al. 2018

Concurrency and Computation

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Photonics technology has become a promising and viable alternative for both on-chip and off-chip interconnection networks of future Exascale systems. Nevertheless, this technology is not mature enough yet in this context, so research efforts focusing on photonic networks are still required to achieve realistic suitable network implementations. In this regard, system-level photonic network simulators can help guide designers to assess the multiple design choices. Most current research is done on electrical network simulators, whose components work widely different from photonics components. In this work, we summarize and compare the working behavior of both technologies which includes the use of optical routers, wavelength-division multiplexing and circuit switching among others. After implementing them into a well-known simulation framework, an extensive simulation study has been carried out using realistic photonic network configurations with synthetic and realistic traffic. Experimental results show that, compared to electrical networks, optical networks can reduce the execution time of the studied real workloads in almost one order of magnitude. Our study also reveals that the photonic configuration highly impacts on the network performance, being the bandwidth per channel and the message length the most important parameters. KEYWORDS interconnection networks, photonic technology, simulation framework 1 INTRODUCTION The most powerful supercomputers in the world 1 are ranked by their computational power in terms of floating-point operations executed per second (FLOPS). The Sunway TaihuLight, the recent supercomputer leading the list at November 2017, realizes by 93 PetaFlops (10 15 ) with 10.5 million cores. The Top500 list tracks the computational power of supercomputers since 1971, and according to the current growing compu-tational trend, it is expected that supercomputers will break the ExaFlop (10 18 ) barrier by 2020. Reaching this target, however, is challenging and requires from multiple simultaneous solutions addressing, among others, computation at chip level (nodes of the system), data movement across the system, distributed storage, energy management, etc.From the aforementioned challenges, the data movement challenge is probably the most critical to be achieved, mainly due to the increasing number of computing nodes, and therefore, the increasing communication requirements. Exascale networks will count with thousands of computing nodes, so data transmission among them becomes a major design concern, and new requirements rise not only in terms of throughput but also in energy demands. In such systems, the underlying network technology 2,3 is a critical design choice, and this is the focus of the European ExaNeSt, project which is currently being developed (see Section 2.1 for more details).In this regard, photonics interconnects, both on-chip and off-chip, have emerged as a worth alternative technology addressing the key constraints of traditional electrical networks. This technology provides much m...

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A CAM-Free Exascalable HPC Router for Low-Energy Communications

Cited by 7 publications

References 21 publications

Enabling Standalone FPGA Computing

Enabling Standalone FPGA Computing

On the effects of allocation strategies for exascale computing systems with distributed storage and unified interconnects

Modeling and analysis of the performance of exascale photonic networks

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