Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00375)
DOI: 10.1109/fpga.1999.803663
|View full text |Cite
|
Sign up to set email alerts
|

A CAD suite for high-performance FPGA design

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1
1
1

Citation Types

0
31
0

Publication Types

Select...
4
3
1

Relationship

0
8

Authors

Journals

citations
Cited by 81 publications
(31 citation statements)
references
References 9 publications
0
31
0
Order By: Relevance
“…As discussed in [2], the JHDL design, simulation, and execution environment provides a unified view of a design's simulation and hardware execution-they look the same in the various design views. During simulation, the simulator itself is responsible for keeping track of the values and state of the circuit elements in a design.…”
Section: Jhdl and Hardware Executionmentioning
confidence: 99%
See 1 more Smart Citation
“…As discussed in [2], the JHDL design, simulation, and execution environment provides a unified view of a design's simulation and hardware execution-they look the same in the various design views. During simulation, the simulator itself is responsible for keeping track of the values and state of the circuit elements in a design.…”
Section: Jhdl and Hardware Executionmentioning
confidence: 99%
“…In supporting hardware debugging in the JHDL [1,2] design environment, we have found that knowing how design elements from the user's logical design were mapped to their counterparts in the FPGA physical implementation is quite important. With only a partial mapping from the logical to the physical, we would not be able to provide users of JHDL with a complete view of what their circuit is doing during hardware execution via FPGAs' readback mechanism [3,4].…”
Section: Introductionmentioning
confidence: 99%
“…The compiler originally targeted the Wildforce board, as did the other two compilers, but was later abstracted so that it might support other boards as well, although we did not retarget the compiler to any other XC4000 based configurable computing boards. The C4PL library for this compiler was written in JHDL [6,7] and included the Supercell module generator, as well as the circuits used to convert image data to/from a raster stream readable by the FOA circuit.…”
Section: First-level Compilermentioning
confidence: 99%
“…In addition, recent work (Marwedel and Sirocic, 2003;Ferreira et al, 2004;Rodrigues and Cardoso, 2005) have shown that Hades-based environment can handle many computer architecture subjects, and still have a good performance and easy interaction with tools and environments. Another Java-based environment is JHDL (Hutchings et al, 1999), which is a structurally based Hardware Description Language (HDL) implemented with Java. Our environment differs from JHDL structural approach, and proposes a behavior and/or structural description.…”
Section: Related Workmentioning
confidence: 99%