A-CACHE: Alternating Cache Allocation to Conduct Higher Endurance in NVM-Based Caches

Farbeh, Hamed; Monazzah, Amir Mahdi Hosseini; Aliagha, Ensieh; Cheshmikhani, Elham

doi:10.1109/tcsii.2018.2881175

Cited by 16 publications

(9 citation statements)

References 28 publications

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“…Note that the endurance cycles of PCM and STT-MRAM, respectively, are about 3-4 and 7-8 orders of magnitude more than that of flash memory. Endurance problems of NVM can be further referenced in other studies [27], [29], [30].…”

Section: Discussionmentioning

confidence: 99%

Analysis of Smartphone I/O Characteristics — Toward Efficient Swap in a Smartphone

Kim¹,

Bahn²

2019

IEEE Access

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Section: Discussionmentioning

confidence: 99%

Analysis of Smartphone I/O Characteristics — Toward Efficient Swap in a Smartphone

Kim¹,

Bahn²

2019

IEEE Access

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“…In [39], an encoding scheme is proposed for reducing the frequency of bitflips in NVM-based caches. In [38], contents in NVMbased instruction and data caches are uniformly and periodically interchanged with the dedicated cache controller. Although these schemes may mitigate WDEs, these schemes do not specifically consider the characteristics and vulnerability patterns of WDEs.…”

Section: Discussion: Applicability Of Wl-wdmentioning

confidence: 99%

WL-WD: Wear-Leveling Solution to Mitigate Write Disturbance Errors for Phase-Change Memory

et al. 2022

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Phase-change memory (PCM) is a promising non-volatile memory device due to its attractive properties such as fast access time and byte-addressability. However, PCM is still difficult to be used as a main memory because of its weakness in endurance and write disturbance. Conventional wearleveling algorithms have attempted to handle short endurance, but they have not addressed the issue of write disturbance even though both issues are caused by write operations to PCM. This paper proposes a wear-leveling algorithm that addresses not only the endurance, but also the write disturbance. From the observation that the write disturbance errors and short endurance issues mostly take place in hot addresses, the proposed algorithm first detects hot addresses and maps them to 'hot' regions, which are customized memory regions designed to be robust to write disturbance errors and to support effective wear-leveling. The 'hot' region is not fixed to a specific part, but it moves over an entire memory space to make every cell belong to 'hot' regions in a uniform manner. On the other hand, cold addresses are mapped in 'normal' memory regions by simple linear mapping to reduce the hardware overhead. The proposed algorithm can reduce the write disturbance errors by more than 70% with only a slight instruction per cycle (IPC) degradation. Moreover, the wear-leveling performance is also enhanced by more than 3% compared to other wear-leveling algorithms.

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“…1(a). An MTJ consists of two ferromagnetic layers separated by a thin oxide barrier layer [5], [16], [34]. These layers as depicted in Fig.…”

Section: A Stt-mram Cell Basicsmentioning

confidence: 99%

“…STT-MRAM caches benefit from non-volatility, higherdensity, near-zero leakage power, and immunity to radiationinduced particle strikes [? ], [14]- [16]. However, STT-MRAM reliability is a major challenge for its applicability in LLCs.…”

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confidence: 99%

A System-Level Framework for Analytical and Empirical Reliability Exploration of STT-MRAM Caches

2020

Self Cite

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𝑆 𝑝𝑖𝑛-𝑇𝑟𝑎𝑛𝑠 𝑓 𝑒𝑟 𝑇 𝑜𝑟𝑞𝑢𝑒 𝑀𝑎𝑔𝑛𝑒𝑡𝑖𝑐 𝑅 𝐴𝑀 (STT-MRAM) is known as the most promising replacement for SRAM technology in large 𝐿𝑎𝑠𝑡-𝐿𝑒𝑣𝑒𝑙 𝐶𝑎𝑐ℎ𝑒 memories (LLCs). Despite its high-density, non-volatility, near-zero leakage power, and immunity to radiation as the major advantages, STT-MRAMbased cache memory suffers from high error rates mainly due to 𝑟𝑒𝑡𝑒𝑛𝑡𝑖𝑜𝑛 𝑓 𝑎𝑖𝑙𝑢𝑟𝑒, 𝑟𝑒𝑎𝑑 𝑑𝑖𝑠𝑡𝑢𝑟𝑏𝑎𝑛𝑐𝑒, and 𝑤𝑟𝑖𝑡𝑒 𝑓 𝑎𝑖𝑙𝑢𝑟𝑒. Existing studies are limited to estimate the rate of 𝑜𝑛𝑙 𝑦 one or two of these error types for STT-MRAM cache. However, the overall vulnerability of STT-MRAM caches, which its estimation is a must to design cost-efficient reliable caches, has not been offered in none of previous studies.In this paper, we propose a system-level framework for reliability exploration and characterization of errors behavior in STT-MRAM caches. To this end, we formulate the cache vulnerability considering the inter-correlation of the error types including retention failure, read disturbance, and write failure as well as the dependency of error rates to workloads behavior and 𝑃𝑟𝑜𝑐𝑒𝑠𝑠 𝑉 𝑎𝑟𝑖𝑎𝑡𝑖𝑜𝑛𝑠 (PVs). Our analysis reveals that STT-MRAM cache vulnerability is highly workload-dependent and varies by orders of magnitude in different cache access patterns. Our analytical study also shows that this vulnerability divergence significantly increases by process variations in STT-MRAM cells. To take the effects of system workloads and PVs into account, we implement the error types in gem5 full-system simulator. The experimental results using a comprehensive set of multi-programmed workloads from SPEC CPU2006 benchmark suite on a quad-core processor show that the total error rate in a shared STT-MRAM LLC varies by 32.0x for different workloads. A further 6.5x vulnerability variation is observed when considering PVs in the STT-MRAM cells. In addition, the contribution of each error type in total LLC vulnerability highly varies in different cache access patterns and moreover, error rates are differently affected by PVs. The proposed analytical and empirical studies can significantly help system architects for efficient utilization of error mitigation techniques and designing highly reliable and low-cost STT-MRAM LLCs.

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A-CACHE: Alternating Cache Allocation to Conduct Higher Endurance in NVM-Based Caches

Cited by 16 publications

References 28 publications

Analysis of Smartphone I/O Characteristics — Toward Efficient Swap in a Smartphone

Analysis of Smartphone I/O Characteristics — Toward Efficient Swap in a Smartphone

WL-WD: Wear-Leveling Solution to Mitigate Write Disturbance Errors for Phase-Change Memory

A System-Level Framework for Analytical and Empirical Reliability Exploration of STT-MRAM Caches

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