A Built-Off Self-Repair Scheme for Channel-Based 3D Memories

Liu, Hsuan-Hung; Lin, Bing-Yang; Wu, Cheng‐Wen; Chiang, Wan-Ting; Lee, Mincent; Lin, Hong‐Ping; Peng, Ching-Nen; Wang, Min-Jer

doi:10.1109/tc.2017.2667645

Cited by 5 publications

(9 citation statements)

References 19 publications

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“…When only the row spare lines and column spare lines are used in each layer, the ESP [18] and the BRANCH [22] is used for analyzing faulty cells. For the redundant spares on the base die, the CSA [34] is compared with the proposed BIRA. This BIRA has the best performance among BIRAs with redundant spares located on the base die [31]- [34].…”

Section: Resultsmentioning

confidence: 99%

“…For the redundant spares on the base die, the CSA [34] is compared with the proposed BIRA. This BIRA has the best performance among BIRAs with redundant spares located on the base die [31]- [34]. It uses SRAM modules to repair faults based on a configurable spare allocation algorithm [34].…”

Section: Resultsmentioning

confidence: 99%

“…These three features have tradeoff relationships with each other. Improving them all is the goal of BIRA research [16]- [34].…”

Section: Introductionmentioning

confidence: 99%

“…However, because only the sharing of redundant spares between neighboring layers is possible, there is a structural limitation to make full use of all redundant spares in 3D memory. The whole share redundancy scheme, redundant spares are shared by all memory layers [31]- [34]. Most structures of this type place the redundant spares in the free space located in the base die in 3D stacked memory [37].…”

Section: Introductionmentioning

confidence: 99%

“…The shape of these multiple word-sized redundant spares used for repair in CoCRA depends on the masked addresses. The configurable spare allocation (CSA), redundant spares of the BIRA are shaped according to the pattern of faults [34]. This BIRA shows the highest repair rate for cluster faults, and it can effectively repair not only cluster faults, but also line faults compared to other previous works.…”

Section: Introductionmentioning

confidence: 99%

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Effective Spare Line Allocation Built-in Redundancy Analysis With Base Common Spare for Yield Improvement of 3D Memory

2021

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The memory cell density and memory capacity have been increased for obtaining larger and faster memory. However, this threatens the memory reliability by increasing the probability of faulty cell generation. In this paper, a fast and small-area built-in redundancy analysis (RA) for the post-bond repair process in 3D memory is proposed. Spare line allocation is the structure for memory repair which the most widely used. However, the spare line structure that replaces the entire line which contains faults in each memory layer occurs inefficiency in repairing a small number of faults, including single faults, and it is difficult to share spares between layers. The proposed idea is to use spare line to repair line faults according to the characteristics of it, and to complement the structural limitations by proposing a new redundant spare. This is base common spare located on the base die, and it can be shared across all layers. The proposed BIRA improves the efficiency of spare lines with two complementary spare resource structures, achieving a short repair time and high repair rate. The proposed BIRA achieves 100% repair rate when there are at least 2 times more faults than the previous works with the same hardware overhead. In addition, it takes only at most 80% of the analysis time compared to the previous works, and as the number of faults increases, the analysis time reduction becomes greater compared to the previous works.INDEX TERMS built-in redundancy analysis (BIRA), built-in self-repair (BISR), built-in self-test (BIST), memory repair, repair rate, yield improvement

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

“…These three features have tradeoff relationships with each other. Improving them all is the goal of BIRA research [16]- [34].…”

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Effective Spare Line Allocation Built-in Redundancy Analysis With Base Common Spare for Yield Improvement of 3D Memory

2021

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A Novel Built-In Self-Repair Scheme for 3D Memory

Chang

Yao

et al. 2019

IEEE Access

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Three-dimensional (3D) memory products based on through silicon via (TSV) are widely developed to fulfill the ever-increasing demands of per unit area storage capacity. The yield is still one of the critical challenges for 3D memory. Redundancy technique is now widely used in industry to improve yield. How to reduce the overhead of redundancy by improving the utilization of redundancy is important to 3D memory. In this paper, we propose a row/column block-based mapping technique for 3D memory built-in self-repair scheme to improve the utilization of redundancy and low hardware overhead. Each row/column is divided into row/column block and the mapping can be performed at row/column-block level instead of the original row/column level. Therefore, more faulty cells can be clustered into the same row/column. Based on the proposed technology, a 3D-essential spare pivoting (ESP) algorithm is also proposed for the allocation of redundant rows and columns, and the area overhead of this algorithm is particularly low. The experimental results show that on an average the repair ratio of our proposed scheme is much better than the fault clustering technique by 12% and the redundancy-cost can reduce 23%.

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Efficient Repair Analysis Algorithm Exploration for Memory With Redundancy and In-Memory ECC

Sun

Xin

et al. 2021

IEEE Trans. Comput.

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A Built-Off Self-Repair Scheme for Channel-Based 3D Memories

Cited by 5 publications

References 19 publications

Effective Spare Line Allocation Built-in Redundancy Analysis With Base Common Spare for Yield Improvement of 3D Memory

Effective Spare Line Allocation Built-in Redundancy Analysis With Base Common Spare for Yield Improvement of 3D Memory

A Novel Built-In Self-Repair Scheme for 3D Memory

Efficient Repair Analysis Algorithm Exploration for Memory With Redundancy and In-Memory ECC

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