A built-in self-testing approach for minimizing hardware overhead

Chiu, S.; Papachristou, C.

doi:10.1109/iccd.1991.139898

Cited by 40 publications

(20 citation statements)

References 10 publications

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“…Almost all of the BIST-based approaches assume a scan design methodology since random testing is not well suited for sequential circuits [17]- [19], [31]. Also, almost all of the ATPG-based behavioral test synthesis approaches, with the exception of methods proposed in [23] and [25], assume the use of scan registers to make the data paths testable.…”

Section: B High-level Dft Techniquesmentioning

confidence: 99%

“…Recently, several behavioral-level design and synthesis approaches have been proposed to generate easily testable data paths for both built-in-self-test (BIST)-based testing methodology [17]- [20] and automatic test-pattern generation (ATPG) methods [21]- [28]. These techniques either modify the behavioral description of a design to improve the testability of the resulting circuit [21], [27], [28] or consider testability as one of the design objectives during the behavioral synthesis process.…”

Section: B High-level Dft Techniquesmentioning

confidence: 99%

See 1 more Smart Citation

Nonscan design-for-testability techniques using RT-level design information

Dey

Potkonjak²

1997

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-This paper presents nonscan design-for-testability (DFT) techniques applicable to register-transfer (RT)-level data path circuits. Knowledge of high-level design information, in the form of the RT-level structure, as well as the functions of the RT-level components is utilized to develop effective nonscan DFT techniques. Instead of conventional techniques of selecting flip-flops (FF's) to make controllable/observable, execution units (EXU's) are selected using the EXU S-graph introduced in this paper. Controllability/observability points can be implemented using register files and constants.We introduce the notion of k k k-level controllable and observable loops and demonstrate that it suffices to make all the loops k k k-level controllable/observable, k k k> > >0, to achieve very high test efficiency.

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Section: B High-level Dft Techniquesmentioning

confidence: 99%

Section: B High-level Dft Techniquesmentioning

confidence: 99%

Nonscan design-for-testability techniques using RT-level design information

Dey

Potkonjak²

1997

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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show abstract

“…In [9][10][11], self-loop reduction in data path is targeted to solve problems in BIST. In [9], two allocation methods are presented to map a given scheduled data flow graph (DFG) on a selftestable data path.…”

Section: Related Workmentioning

confidence: 99%

A parameterized graph-based framework for high-level test synthesis

2006

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“…Several high level synthesis for testability approaches have been proposed to generate easily testable data paths for both Built-In-SelfTest (BIST)-based testing methodology [1,2,3], and Automatic Test Pattern Generation (ATPG) methods [4,5,6,7]. However, almost all BIST-based approaches assume a scan design methodology since random testing is not well-suited for sequential circuits.…”

Section: Introductionmentioning

confidence: 99%