A built-in self-test scheme for the post-bond test of TSVs in 3D ICs

SUMMARY A design-for-testability method and an electrical interconnect test method are proposed to detect open defects occurring at interconnects among dies and input/output pins in 3D stacked ICs. As part of the design method, an nMOS and a diode are added to each input interconnect. The test method is based on measuring the quiescent current that is made to flow through an interconnect to be tested. The testability is examined both by SPICE simulation and by experimentation.

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“…When a resistive open defect of R f occurs at b, I Dt flows that is expressed by (10). Thus, I Dt specified by P2 in Fig.…”

Section: Comparison To [18]mentioning

confidence: 99%

A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs

Ashikin

Hashizume

Yotsuyanagi

et al. 2018

IEICE Trans. Inf. & Syst.

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“…From this perspective, TSV BIST techniques (e.g., [23]) are insufficient for in-field test and diagnosis because they target on faults occurred in individual TSV structure (and often consider TSV open/short only) instead of delay faults of circuit paths with TSVs. For example, as discussed in Section 2.2, using a fault-free TSV to replace a faulty one does not necessarily lead to a valid repair solution because of the unknown signal timing slack changes with circuit aging.…”

Section: Online Test and Diagnosismentioning

confidence: 99%

On effective and efficient in-field TSV repair for stacked 3D ICs

Jiāng

et al. 2013

Proceedings of the 50th Annual Design Automation Conference

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Three-dimensional (3D) integration based on through-silicon-vias (TSVs) is rapidly gaining traction for industry adoption. However, manufacturing processes for TSVs have been shown to introduce new failure mechanisms. In particular, thermo-mechanical stress and electromigration introduce reliability threats for TSVs, e.g., voids and interfacial cracks, which can lead to hard-to-predict timing errors on critical paths with TSVs, thereby resulting in accelerated chip failure in the field. Burn-in for screening latent defects during manufacturing is expensive and its effectiveness for new TSV defect types has yet to be thoroughly characterized. We describe a reconfigurable in-field repair solution that is able to effectively tolerate latent TSV defects through the judicious use of spares. The proposed solution includes a reconfigurable repair architecture that enables spare TSV sharing between TSV grids, and the corresponding in-field repair algorithms. The effectiveness and efficiency of our proposed solution is evaluated using 3D benchmark designs.

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“…Since there are many TSVs inside a 3D IC, it takes a long test time when the 3D IC is tested by the test method. Thus, various kinds of Design for Testability(DFT) methods and built-in test ones have been proposed so as to shorten the test time [4,5,6,7,8]. [2].…”

Section: Introductionmentioning

confidence: 99%

A testable design for electrical interconnect tests of 3D ICs

Odoriba

Umezu

Hashizume

et al. 2015

2015 International Conference on Electronics Packaging and iMAPS All Asia Conference (ICEP-IAAC)

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A testable design method for electrical testing is proposed in this paper to detect open defects occurring at interconnects between dies in a 3D IC and locate the defective interconnects. An IEEE 1149.1 test circuit is utilized to provide a test input vector to a targeted interconnect in the electrical tests. Feasibility of the electrical tests is evaluated by Spice simulation. It is shown by the experiments that a hard open defect and a resistive open defect can be detected at a test speed of 1GHz.

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A built-in self-test scheme for the post-bond test of TSVs in 3D ICs

Cited by 66 publications

References 16 publications

A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs

A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs

On effective and efficient in-field TSV repair for stacked 3D ICs

A testable design for electrical interconnect tests of 3D ICs

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