A built-in self-test circuit with timing margin test function in a 1 Gbit synchronous DRAM

Sakashita, N.; Okuda, F.; Shimomura, K.; Shimano, Hiroki; Hamada, M.; Tada, Tetsuo; Komori, S.; Kyuma, Kazuo; Yasuoka, Akihiko; Abe, Haruhiko

doi:10.1109/test.1996.556977

Cited by 12 publications

(2 citation statements)

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“…On the other hand, due the limited external access, testing embedded DRAMs is an even more challenging problem than testing monolithic DRAM chips. Here, a number of built-in self-test approaches which have been proposed in the literature can help to develop solutions [1], [2], [4], [5], [6], [7], [8], [10], [14], [15], [16], [18], [19], [21], [23], [28]. A typical BIST architecture is shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

Efficient online and offline testing of embedded DRAMs

Hellebrand

Wunderlich

Ivaniuk

et al. 2002

IEEE Trans. Comput.

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AbstractÐThis paper presents an integrated approach for both built-in online and offline testing of embedded DRAMs. It is based on a new technique for output data compression which offers the same benefits as signature analysis during offline test, but also supports efficient online consistency checking. The initial fault-free memory contents are compressed to a reference characteristic and compared to test characteristics periodically. The reference characteristic depends on the memory contents, but unlike similar characteristics based on signature analysis, it can be easily updated concurrently with WRITE operations. This way, changes in memory do not require a time consuming recomputation. The respective test characteristics can be efficiently computed during the periodic refresh operations of the dynamic RAM. Experiments show that the proposed technique significantly reduces the time between the occurrence of an error and its detection (error detection latency). Compared to error detecting codes (EDC) it also achieves a significantly higher error coverage at lower hardware costs. Therefore, it perfectly complements standard online checking approaches relying on EDC, where the concurrent detection of certain types of errors is guaranteed, but only during READ operations accessing the erroneous data.

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Section: Introductionmentioning

confidence: 99%

Efficient online and offline testing of embedded DRAMs

Hellebrand

Wunderlich

Ivaniuk

et al. 2002

IEEE Trans. Comput.

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“…One of the general solutions is BIST (Built-in self test). A number of theoretical and practical BIST approaches have been proposed [1][2][3][4][5][6][7]. Another important issue in memory testing field is the application of the periodic or transparent testing which ensures high reliability of storage data during a lifetime of operation.…”

Section: Introductionmentioning

confidence: 99%

DPSC SRAM transparent test algorithm

Kim

Kang

Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).

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We present a new transparent SRAM test algorithm, which uses dynamic power supply current. The proposed test scheme employs the dynamic power supply current instead of making signatures, so that it does not need the additional steps and additional hardware to generate signature. This paper describes how to convert a traditional March algorithm to a transparent one. The transformed algorithm is much simpler and the test time can be reduced very much. In addition, it can detect some additional faults that the original algorithm cannot detect.

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