A Brief Introduction to Time-to-Digital and Digital-to-Time Converters

Roberts, G.W.; Ali-Bakhshian, M.

doi:10.1109/tcsii.2010.2043382

Cited by 152 publications

(89 citation statements)

References 10 publications

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“…Except for the accurate value of ω 1 in (10), the other approximations for ω c , ω 1 , and ω 1 in (10), (15), and (24) have been previously reported [2], [6]- [9].…”

Section: Sinusoidal Input Signalmentioning

confidence: 93%

“…In order to solve the series in (6) and (7), we should have an understanding about the loop filter. In most of the conventional filters that are generally used in ASDMs (like the ones used in the next section as examples or in [9]) for ω ω 1 we have:…”

Section: A General Theorymentioning

confidence: 99%

“…Such a representation is very convenient for low voltage environments and the corresponding two-level output signal can easily be processed by simple (pseudo-digital) circuits [3], [6].…”

Section: Introductionmentioning

confidence: 99%

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Analytical Expressions for the Distortion of Asynchronous Sigma–Delta Modulators

Babaie-Fishani

Keymeulen

Rombouts

2013

IEEE Trans. Circuits Syst. II

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Abstract-This work investigates the commonly used Asynchronous Sigma Delta Modulator which consists of a schmitttrigger and a continuous time loop filter. A detailed analysis is presented to accurately predict the distortion of such modulators. The extracted expressions are compared with simulation results and they illustrate an excellent match. The results are also compared with a previous work by Roza and they show a drastic improvement in accuracy.

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“…Except for the accurate value of ω 1 in (10), the other approximations for ω c , ω 1 , and ω 1 in (10), (15), and (24) have been previously reported [2], [6]- [9].…”

Section: Sinusoidal Input Signalmentioning

confidence: 93%

Section: A General Theorymentioning

confidence: 99%

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Analytical Expressions for the Distortion of Asynchronous Sigma–Delta Modulators

Babaie-Fishani

Keymeulen

Rombouts

2013

IEEE Trans. Circuits Syst. II

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“…Numerous designs have been proposed for fully digital voltage sensors and analog-to-digital converters (ADCs) because they are widely preferred to achieve noise immunity [4][5][6][7]. However, to the best of our knowledge, a FinFET-based digital voltage sensor has yet to be developed.…”

Section: Introductionmentioning

confidence: 99%

Low-Power Fully Digital Voltage Sensor using 32-nm FinFETs

Nguyen¹,

Kim

2016

IEIE Transactions on Smart Processing and Computing

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Abstract:In this paper, a design for a fully digital voltage sensor using a 32-nm fin-type field-effect transistor (FinFET) is presented. A new characteristic of the double gate p-type FinFET (p-FinFET) is examined and proven appropriate for sensing voltage variations. On the basis of this characteristic, a novel technique for designing low-power voltage-to-time converters is presented. Then, we develop a digital voltage sensor with a voltage range of 0.7 to 1.1V at a 50-mV resolution. The performance of the proposed sensor is evaluated under a range of voltages and process variations using Simulation Program with Integrated Circuit Emphasis (SPICE) simulations, and the sensor is proven capable of operating under ultra-low power consumption, high linearity, and fairly high-frequency conditions (i.e., 100 MHz).

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“…The original counter-based solutions had proven to be limited by the clock period [4], so sub-clock period resolution TDCs were proposed. Taking the analogy from analog-todigital converters, the flash-type TDCs [5] are based on delay line(s) with identical delay stages like buffers or inverters.…”

Section: Introductionmentioning

confidence: 99%

A CMOS 0.23pj Freeze Vernier Time-To-Digital Converter

et al. 2013

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Abstract-A novel Time-to-Digital Converter architecture for high resolution and low power is proposed. The Freeze Vernier Delay Line is a Vernier-type TDC, where the state of the slow delay line can be frozen by the fast delay line, omitting the powerhungry time capture elements like D-registers or arbiters that are usually employed in a Vernier TDC. The two main issues of the design, the charge kickback between the delay lines and the imperfect freezing are solved with extra circuitry. The overall TDC consists of inverters and transmission gates only. A proof-ofconcept design has been simulated in 90nm CMOS with a typical resolution of 10.05 ps, a dynamic energy consumption of 0.232 pJ per conversion and an area of 10.503 µm 2 .

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A Brief Introduction to Time-to-Digital and Digital-to-Time Converters

Cited by 152 publications

References 10 publications

Analytical Expressions for the Distortion of Asynchronous Sigma–Delta Modulators

Analytical Expressions for the Distortion of Asynchronous Sigma–Delta Modulators

Low-Power Fully Digital Voltage Sensor using 32-nm FinFETs

A CMOS 0.23pj Freeze Vernier Time-To-Digital Converter

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