2015
DOI: 10.1631/fitee.1500058
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A block zero-padding method based on DCFT for L1 parameter estimations in weak signal and high dynamic environments

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Cited by 8 publications
(8 citation statements)
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“…To compare with CAMDP, SDHT [10] and DCFT [20], called the FFT-based methods, are used. The total number of complex multiplications of the methods can be shown in Table 1.…”
Section: Complexity Analysismentioning
confidence: 99%
See 1 more Smart Citation
“…To compare with CAMDP, SDHT [10] and DCFT [20], called the FFT-based methods, are used. The total number of complex multiplications of the methods can be shown in Table 1.…”
Section: Complexity Analysismentioning
confidence: 99%
“…The probability of bit transitions has been analyzed for improving the detection probability in the article [18]. Since discrete chirp-Fourier transform (DCFT) can be used to improve L5 signal acquisition detection probability [19], we have proposed a block zero-padding method based on DCFT for parameter estimations in weak signal and high dynamic environments in the article [20]. In this way, the post-correlation signal has been coherently post-integrated with the bit sequence stripped off, and the high dynamic parameters have been precisely estimated using the threshold set based on a false alarm probability.…”
Section: Introductionmentioning
confidence: 99%
“…Among methods for initial frequency and chirping rate estimation, the authors in [12,13] proposed frequency estimation methods based on Fractional Fourier transform (FRFT) for high-dynamic applications. In addition, we proposed a frequency estimation method based on discrete chirp-Fourier transform (DCFT) [14]. However, in some high-dynamic applications, more accurate frequency is usually desired.…”
Section: Introductionmentioning
confidence: 99%
“…The most commonly used loop, the phase-locked loop (PLL), has low sensitivity [ 1 ]. Increasing the integration time is a common solution to improve the sensitivity of receivers, such as coherent integration, non-coherent integration and differential integration [ 2 , 3 ]. However, increasing the integration time will reduce the dynamic performance of the phase-locked loop (PLL).…”
Section: Introductionmentioning
confidence: 99%