IEEE GLOBECOM 2007-2007 IEEE Global Telecommunications Conference 2007
DOI: 10.1109/glocom.2007.57
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A Bit-Node Centric Architecture for Low-Density Parity-Check Decoders

Abstract: A bit-node centric decoder architecture for lowdensity parity-check codes is proposed. This architecture performs the optimum sum-product algorithm. A bit node processing unit computes the bit-to-check node messages sequentially, while the computation of the check-to-bit node messages is broken up into several steps. A stand-alone decoder architecture, and a decoder architecture for a concatenated detector-decoder system are presented. The proposed stand-alone decoder architecture requires significantly less m… Show more

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“…The operations of read, write, and begin are performed in parallel with the APP memory, which uses registers. The memory of APP is classified into three portions in the suggested architecture, and the memory of CTV is divided into two parts [41][42][43]. Figure 4 shows the top-level architecture of the proposed 5G LTE-based LDPC decoder.…”
Section: Figure 3 Compressed Format Of Ctv Messagesmentioning
confidence: 99%
“…The operations of read, write, and begin are performed in parallel with the APP memory, which uses registers. The memory of APP is classified into three portions in the suggested architecture, and the memory of CTV is divided into two parts [41][42][43]. Figure 4 shows the top-level architecture of the proposed 5G LTE-based LDPC decoder.…”
Section: Figure 3 Compressed Format Of Ctv Messagesmentioning
confidence: 99%