A BIST scheme for RTL circuits based on symbolic testability analysis

A heuristic for wiring-aware built-in self-test synthesis

“…Our definition of testability of DFG operations is based on the use of symbolic testability analysis [2], [3], which asserts an operation to be testable if there is a guaranteed transparent path from on-chip TPGs to the inputs of the operation for supplying pure test patterns, and a transparent path from the output of the operation to an onchip MISR or BILBO for observing test results. In other words, a DFG operation is testable if its input operands are controllable and its output observable at the same time.…”

“…The approach results in very good designs in terms of area since both geometrical information and testability are simultaneously taken into account during BIST synthesis process. On the other hand, since computation intensive Symbolic Testability Analysis (STA) [7], [2], [3] is performed in each optimization loop, the whole approach is very slow.…”

Integrating self testability with design space exploration by a controller based estimation technique

“…Automatic insertion of BIST into RTL data-path description has been the subject of intensive research over the last few years with considerable success [4,6,7,9]. But the approaches have addressed different levels of abstraction.…”

“…But the approaches have addressed different levels of abstraction. The approaches of [4,7] addressed the testability optimisation at the zone III of Figure 1, while the methods published by [6,7] operated on zones II and III. Other published works like that of [8] gave constructive approaches.…”

A Wiring-Aware Approach to Minimizing Built-in Self-Test Overhead

“…The approach is assisted by a symbolic testability analysis (STA) methodology [4], [5] which identifies hard to test operations. STA is performed at the behavioral level on the SDFG representation of the design.…”