A BIST scheme for RTL controller-data paths based on symbolic testability analysis

Abstract

This paper introduces a novel scheme for testing register-transfer level controller/data paths using built-in self-test (BIST). The scheme uses the controller netlist and the data path of a circuit to extract a test control/data flow (TCDF) which consists of operations mapped to modules in the circuit and variables mapped to registers. This TCDF is used to derive a set of symbolic justification and propagation paths (known as test environment) to test some of the operations and variables present in it. If it becomes difficult to generate such test environments with the derived TCDFs, a few test multiplexers are added at suitable points in the circuit to increase its controllability and observability. This test environment can then be used to exercise a module or register in the circuit with pseudorandom pattern generators which are placed only at the primary inputs of the circuit. The test responses can be analyzed with signature analyzers which are only placed at the primary outputs of the circuit. Every module in the module library is made randompattern testable, whenever possible, using gate-level testability insertion techniques. Finally, a BIST controller is synthesized to provide the necessary control signals to form the different test environments during testing, and a BIST architecture is superimposed on the circuit. Experimental results on a number of industrial and university benchmarks show that high fault coverage (>99%) can be obtained with our scheme in a small number of test cycles at an average area (delay) overhead of only 6.4% (2.5%).

A heuristic for wiring-aware built-in self-test synthesis

“…Our definition of testability of DFG operations is based on the use of symbolic testability analysis [2], [3], which asserts an operation to be testable if there is a guaranteed transparent path from on-chip TPGs to the inputs of the operation for supplying pure test patterns, and a transparent path from the output of the operation to an onchip MISR or BILBO for observing test results. In other words, a DFG operation is testable if its input operands are controllable and its output observable at the same time.…”

“…The approach results in very good designs in terms of area since both geometrical information and testability are simultaneously taken into account during BIST synthesis process. On the other hand, since computation intensive Symbolic Testability Analysis (STA) [7], [2], [3] is performed in each optimization loop, the whole approach is very slow.…”

A DFT method for BIST of RTL data paths based on single‐control testability

“…For almost all of the combinational circuit elements (e.g., adder, subtracter, multiplier, shifter, multiplexer) used in the actual data path, it is known that a high fault detection rate can be obtained for a degeneration fault by using random patterns as test patterns [7], and it can be expected that a high fault detection rate can be obtained by the proposed technique.…”

Test strategies for BIST at the algorithmic and register-transfer levels

“…[1,5,12,8] create a test environment for each module, which consists of a justification path and a propagation path. [4] extends the technique to pseudorandom BIST. Our approach uses the one-to-one property of operations, instead of the identity property, to propagate patterns.…”