A BiCMOS PLL-based data separator circuit with high stability and accuracy

Miyazawa, S.; Horita, R.; Hase, K.; Kato, Kazúo; Kojima, Shinichi

doi:10.1109/4.68125

Cited by 10 publications

(1 citation statement)

References 2 publications

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“…)t 2 n=l + Z Bn sin nwt (2) n=l where coefficients A, and Bn obtained by means of Fourier series analysis are given by 2 [r12 An = ~ a_r/ f(acoso)t)cosncotdt (3) 2 [rt~ B, = -~ j_r/2f(acoswt)sinnwtdt (4) T (= 2zr/w) is the period of the input signal. For an ideal linear circuit, only the fundamental component exists, i.e.…”

Section: So(t) = F(acos~ot)mentioning

confidence: 99%

Analysis and CAD implementation techniques of total harmonic distortion in analog VLSI circuits

Huang

Ismail

Wassenaar

1996

Analog Integr Circ Sig Process

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This paper presents a new methodology to accurately evaluate the total harmonic distortion (THD) behavior of modern integrated circuits. The methodology is general, technology independent and is used to determine large-signal or reactive THD of signal processing circuits operating in the voltage or the current domain. It is based on Fourier series analysis and Parseval's theorem, where numerical integration may be needed to accurately compute THD. For low-frequency THD, the numerical integration can be simplified to a small number of summation without degrading the accuracy. The new methodology is incorporated in a computer-aided environment which accurately estimates THD, and the speed of calculation for many circuit is several orders of magnitude faster than SPICE or other commercial CAD tools. In addition, optimization of transistor sizes to reduce THD can be achieved by incorporating the methodology in an object-oriented CAD tool such as APLAC.

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Section: So(t) = F(acos~ot)mentioning

confidence: 99%

Analysis and CAD implementation techniques of total harmonic distortion in analog VLSI circuits

Huang

Ismail

Wassenaar

1996

Analog Integr Circ Sig Process

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Optimum phase-acquisition technique for charge-pump PLL

Roh

Lee

Kim

1997

IEEE Trans. Circuits Syst. II

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In this paper, we propose a new optimum phaseacquisition algorithm controlling the loop gain of a chargepump PLL (CP-PLL) in the sense of the MMSE criterion. A set of recursive difference equations minimizing rms jitter of output phase is derived to obtain an optimum gear-shifting sequence with a zero-phase start (ZPS) assumption. It is shown that the optimum gear-shifting sequence is independent of the variance of the input phase jitter. A procedure for applying this sequence to the design of CP-PLL circuits is described. Both behavioral simulation and HSPICE circuit-level simulation demonstrate that the proposed design leads to an efficient CP-PLL having both fast acquisition and significant jitter reduction characteristics. The optimal gear-shifting CP-PLL outperforms the conventional CP-PLL's. These methods can be used for clock recovery applications such as data communication receivers, disk drive read/write channels, and local area networks, as well as for other applications requiring very short initial preamble periods.

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Design of ADPLL for both large lock-in range and good tracking performance

Kim

1999

IEEE Trans. Circuits Syst. II

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A BiCMOS PLL-based data separator circuit with high stability and accuracy

Cited by 10 publications

References 2 publications

Analysis and CAD implementation techniques of total harmonic distortion in analog VLSI circuits

Analysis and CAD implementation techniques of total harmonic distortion in analog VLSI circuits

Optimum phase-acquisition technique for charge-pump PLL

Design of ADPLL for both large lock-in range and good tracking performance

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