A Behavior Model of Planar SiC MOSFET Considering Avalanche Breakdown

Wu, Yunyi; Li, Chi; Zheng, Zedong; Wang, Lianzhong; Liu, Tao; Liu, Guojing

doi:10.1007/978-981-99-0631-4_75

Cited by 1 publication

(3 citation statements)

References 15 publications

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Section: Working Principles Of the Proposed Behavior Modelmentioning

confidence: 93%

“…In this section, the modeling of all components and calculation methods of the key parameters in the proposed behavior model will be elaborated on, including the channel current, parasitic junction capacitances, the resistance of N-type drift layer and JFET layer, leakage current, junction temperature, and key physical parameters used in the above calculations such as intrinsic carrier concentration, threshold voltage and carrier mobility. A physically based and accurate methodology for avalanche breakdown voltage calculation has been explored in previous work [54] and it will not be repeated in this section.…”

Section: Models and Calculationsmentioning

confidence: 99%

“…According to the above physical basis, a separate branch made up of a temperature-controlled voltage source U BR and a controlled switch S BR is included to characterize SiC DMOSFET's avalanche breakdown state. Their working principles have been demonstrated in previous work[54].As said in Section 2, from the perspective of external characteristics, the physical process of avalanche failure is similar to a short circuit happening between source and drain. Using the same idea of avalanche breakdown state modeling, as shown in Figure11, the processes of an avalanche failure state are modeled as a separate branch consisting of a temperature-controlled switch S F in the proposed behavior model.…”

mentioning

confidence: 92%

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A Behavior Model of SiC DMOSFET Considering Thermal-Runaway Failures in Short-Circuit and Avalanche Breakdown Faults

Wu,

Li,

Zheng

et al. 2024

Electronics

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Accurate fault simulation and failure prediction have long been challenges for SiC MOSFETs users. This paper presents a behavior model of Silicon Carbide (SiC) double-implanted MOSFET (DMOSFET), considering thermal-runaway failures in short-circuit and avalanche breakdown faults on the basis of cell-level physical processes. The proposed model can simulate the faults with extremely high accuracy and precisely predict SiC DMOSFET’s short-circuit withstand time and critical avalanche energy. By finite-element simulations, cell-level physical processes of short-circuit and avalanche breakdown faults are clarified. The mechanisms of thermal-runaway failures are deeply discussed with references to existing studies. Based on semiconductor and device physics mechanisms, the proposed model is constructed upon a traditional behavior model of SiC MOSFET with several parallel branches that are proposed to describe the thermal-runaway failures during both faults. The Cauer thermal network model is used for estimating junction temperature within it. The proposed model is constructed in Simulink, and it is validated using short-circuit and unclamped inductive switching (UIS) tests.