A BDD-Based Approach to Constructing LFSRs for Parallel CRC Encoding

Dubrova, Elena; Mansouri, Shohreh Sharif

doi:10.1109/ismvl.2012.20

Cited by 10 publications

(6 citation statements)

References 24 publications

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“…Second, we use programmable parallel LFSRs instead of fixed-polynomial parallel LFSRs to improve the reconfigurability of the design. Existing methods for designing parallel LFSRs work only with a fixed generating polynomial [ 20 , 21 ]. In addition to inadequate reconfigurability, fixed-polynomial LFSRs make the system more vulnerable against some well-known security attacks [ 22 ].…”

Section: Preliminariesmentioning

confidence: 99%

From Random Numbers to Random Objects

Zolfaghari

Bibak

Koshiba

2022

Entropy

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Many security-related scenarios including cryptography depend on the random generation of passwords, permutations, Latin squares, CAPTCHAs and other types of non-numerical entities. Random generation of each entity type is a different problem with different solutions. This study is an attempt at a unified solution for all of the mentioned problems. This paper is the first of its kind to pose, formulate, analyze and solve the problem of random object generation as the general problem of generating random non-numerical entities. We examine solving the problem via connecting it to the well-studied random number generation problem. To this end, we highlight the challenges and propose solutions for each of them. We explain our method using a case study; random Latin square generation.

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Section: Preliminariesmentioning

confidence: 99%

From Random Numbers to Random Objects

Zolfaghari

Bibak

Koshiba

2022

Entropy

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“…Similarly, NLFSRs with the degree of parallelization p are constructed by modifying its feedback functions to compute pth power of its transition relation. This may increase in the size of the circuit computing pth power of its transition relation more than p times due to multiplication of non-linear terms [44]. The the expected size of the NLFSR is thus E[NLFSR(n, p)] ≥ 2β log 2 n + α · p · 2 2 log 2 n /(2 log 2 n) ≥ 2β log 2 n + αpn 2 /(2 log 2 n)…”

Section: From (8) We Getmentioning

confidence: 99%

“…More generally, the problem of constructing an NLFSR with the degree of parallelization p can be solved by computing the pth power of the transition relation induced by its feedback functions. However, the size of circuits computing the pth power of the transition relation may grow substantially larger than a factor of p [44].…”

Section: Previous Workmentioning

confidence: 99%

An Algorithm for Constructing a Minimal Register with Non-linear Update Generating a Given Sequence

Dubrova

2014

2014 IEEE 44th International Symposium on Multiple-Valued Logic

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Registers with Non-Linear Update (RNLUs) are a generalization of Non-Linear Feedback Shift Registers (NLFSRs) in which both, feedback and feedforward, connections are allowed and no chain connection between the stages is required. An RNLU can be used to generate any given 2 p -ary sequence, p ≥ 1. In this paper, a new algorithm for constructing RNLUs is presented. Expected size of RNLUs constructed by the presented algorithm is proved to be asymptotically smaller than the expected size of RNLUs constructed by previous algorithms generating the same sequence. The presented algorithm can potentially be useful for applications such as testing, wireless communications, and cryptography.

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“…The typical CRC-16 with the representation of G(x) ¼x 16 þx 15 þx 2 þ x 0 is exemplified in this paper. It is widely used in modems and network protocols [4]. Fig.…”

Section: Introductionmentioning

confidence: 99%