A basic design guide for CMOS folding and interpolating A/D converters-overview and case study

Lin, Kang-Ping; Boom, T.J.J. van den; Stevanovic, N.; Driesen, J.; Hammerschmidt, Dirk; Hosticka, B.J.

doi:10.1109/icecs.1999.812339

Cited by 7 publications

(3 citation statements)

References 7 publications

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“…Folding is not only used in the fine converter but also in the coarse one and the bit synchronization block. The combination of 3-bit coarse converter and 5-bit fine one is chosen for low power [7] . The interpolating factor is set as 8 to save folders.…”

Section: Adc Architecturementioning

confidence: 99%

Low-power CMOS fully-folding ADC with a mixed-averaging distributed T/H circuit

et al. 2009

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This paper describes an 8-bit 125 MHz low-power CMOS fully-folding analog-to-digital converter (ADC). A novel mixed-averaging distributed T/H circuit is proposed to improve the accuracy. Folding circuits are not only used in the fine converter but also in the coarse one and in the bit synchronization block to reduce the number of comparators for low power. This ADC is implemented in 0.5 μm CMOS technology and occupies a die area of 2 × 1.5 mm2. The measured differential nonlinearity and integral nonlinearity are 0.6 LSB/–0.8 LSB and 0.9 LSB/–1.2 LSB, respectively. The ADC exhibits 44.3 dB of signal-to-noise plus distortion ratio and 53.5 dB of spurious-free dynamic range for 1 MHz input sine-wave. The power dissipation is 138 mW at a sampling rate of 125 MHz at a 5 V supply.

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Section: Adc Architecturementioning

confidence: 99%

Low-power CMOS fully-folding ADC with a mixed-averaging distributed T/H circuit

et al. 2009

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“…Comprehensively considering the power dissipation and signal stability [5], the combination of 2-bit coarse converter and 4-bit fine one is a good trade-off and adopted. Folding circuits are not only used in fine converter but also in coarse one for low power dissipation.…”

Section: Introductionmentioning

confidence: 99%

Low-Power CMOS Fully-Folding ADC with a Novel Bit Synchronization Architecture

Liu

Jia

et al. 2006

2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings

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A 6-bit 250MHz low-power CMOS fully-folding analog-to-digital converter is designed in a 0.5µm standard digital CMOS process. Folding circuits are not only used in fine converter but also in coarse one. A novel bit synchronization architecture also based on folding circuits is presented to reduce the number of comparators for bit synchronization and simplify the logic design. The total power dissipation is 34mW at a 5V supply.

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“…So to extract the advantages of digital signal processing, there is a trend of shifting signal processing from analog to more efficient digital domain and dealing with the analog signals only in the input-output stages. This has resulted in the requirement of smart converters between analog and digital signals to cope up with the evolution of technology [3].…”

Section: Introductionmentioning

confidence: 99%

Design, Implementation and Analysis of Flash Adc Architecture With Differential Amplifier as Comparator Using Custom Design Approach

Lakkannavar

Shirakol

Hosur

2012

IJESS

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Analog-to-Digital Converters (ADCs) are useful building blocks in many applications such as a data storage read channel and an optical receiver because they represent the interface between the real world analog signal and the digital signal processors. Many implementations have been reported in the literature in order to obtain high-speed analog-todigital converters (ADCs). In this paper an effort is made to design 4-bit Flash Analog to Digital Converter [ADC] using 180nm cmos technology. For high-speed applications, a flash ADC is often used. Resolution, speed, and power consumption are the three key parameters for an Analog-to-Digital Converter (ADC). The integrated flash ADC is operated at 4-bit precision with analog input voltage of 0 to 1.8V. The ADC has been designed, implemented & analysed in standard gpdk180nm technology library using Cadence tool.

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A basic design guide for CMOS folding and interpolating A/D converters-overview and case study

Cited by 7 publications

References 7 publications

Low-power CMOS fully-folding ADC with a mixed-averaging distributed T/H circuit

Low-power CMOS fully-folding ADC with a mixed-averaging distributed T/H circuit

Low-Power CMOS Fully-Folding ADC with a Novel Bit Synchronization Architecture

Design, Implementation and Analysis of Flash Adc Architecture With Differential Amplifier as Comparator Using Custom Design Approach

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