A Bandwidth-Optimized Routing Algorithm for Hybrid FPGA Networks-on-Chip

Patil, Shivukumar B.; Liu, Tianqi; Tessier, Russell

doi:10.1109/fccm.2018.00013

Cited by 5 publications

(2 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…During the path selection step, they use a backtracking algorithm to explore the path diversity and during the slot allocation step, path-overlapped VCs must be configured such that no conflict occurs and their bandwidth requirements are satisfied. In [29], Patil et al utilize a multi-iteration routing algorithm to combine path and time slot selection in a single pass. Instead of the dimension-ordered routing, their approach takes any available shortest path from source to destination and uses multiple rip-up and reroute passes to eliminate the effects of network ordering.…”

Section: Tdm Routing Algorithmmentioning

confidence: 99%

Flexible and Efficient QoS Provisioning in AXI4-Based Network-on-Chip Architecture

Wang

2022

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

We propose a Network-on-Chip (NoC)-based whole system design, whose communication architecture is compatible with the AMBA AXI4 protocol and supports high-performance multiple Quality-of-Service (QoS) schemes. In our system, the network interface (NI) between the NoC and the master/slave node is proposed to make the NoC architecture independent from the AXI4 protocol via message format conversion between the AXI4 signal format and the packet format, offering high flexibility to the NoC design. Besides, a QoS inheritance mechanism is applied in the slave-side NI to support QoS during packets' round-trip transfer in the NoC. The NoC system contains Time Division Multiplexing (TDM) and Virtual Channel (VC) subnetworks to apply multiple QoS schemes to AXI4 signals with different QoS tags and the NI is responsible for signals distribution between two subnetworks. Besides, a traffic converter is proposed in each NI to balance the traffic between the two subnetworks when necessary. The experimental results show that our proposed architecture ensures a high-throughput and lowlatency NoC system. By applying traffic converter, the packet latency can be improved.

show abstract

Section: Tdm Routing Algorithmmentioning

confidence: 99%

Flexible and Efficient QoS Provisioning in AXI4-Based Network-on-Chip Architecture

Wang

2022

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

show abstract

“…This routing algorithm can reduce total wire-length and increase the maximum clock frequency at the same time. Wang et al propose a new approach [15] based on the PathFinder algorithm. They only reroute illegal paths during each routing iteration and can reduce 68.5% routing runtime on average.…”

Section: Related Workmentioning

confidence: 99%

A routing algorithm for FPGAs with time-multiplexed interconnects

Luo¹,

Chen²,

Ha³

2020

J. Semicond.

View full text Add to dashboard Cite

Previous studies show that interconnects occupy a large portion of the timing budget and area in FPGAs. In this work, we propose a time-multiplexing technique on FPGA interconnects. In order to fully exploit this interconnect architecture, we propose a time-multiplexed routing algorithm that can actively identify qualified nets and schedule them to multiplexable wires. We validate the algorithm by using the router to implement 20 benchmark circuits to time-multiplexed FPGAs. We achieve a 38% smaller minimum channel width and 3.8% smaller circuit critical path delay compared with the state-of-the-art architecture router when a wire can be time-multiplexed six times in a cycle.

show abstract