A Banded Smith-Waterman FPGA Accelerator for Mercury BLASTP

Harris, Brandon; Jacob, Arpith C.; Lancaster, Joseph M.; Buhler, Jeremy; Chamberlain, Roger D.

doi:10.1109/fpl.2007.4380764

Cited by 33 publications

(11 citation statements)

References 8 publications

(5 reference statements)

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“…Each type of hardware accelerator, such as FPGA or GPU, provides substantial performance improvement for the applications within its target domain. Image processing [De Ruijsscher et al 2006], data mining [Baker and Prasanna 2005], and bioinformatics [Harris et al 2007] are examples of applications with hardware implementations on FPGA and K-means [Che et al 2008], AES encryption [Yamanouchi 2007], and network packet processing [Smith et al 2009] are examples of GPU accelerated applications. Heterogeneous architectures like Cray XD1 [Fahey et al 2005] and SGI Altix 4700 [SGI 2008] employ FPGAs as accelerators, whereas nVidia Tesla [Lindholm et al 2008] employs GPUs for acceleration.…”

Section: Introductionmentioning

confidence: 99%

A dynamic self-scheduling scheme for heterogeneous multiprocessor architectures

Belviranlı

Bhuyan

Gupta

2013

ACM Trans. Archit. Code Optim.

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Today's heterogeneous architectures bring together multiple general-purpose CPUs and multiple domainspecific GPUs and FPGAs to provide dramatic speedup for many applications. However, the challenge lies in utilizing these heterogeneous processors to optimize overall application performance by minimizing workload completion time. Operating system and application development for these systems is in their infancy. In this article, we propose a new scheduling and workload balancing scheme, HDSS, for execution of loops having dependent or independent iterations on heterogeneous multiprocessor systems. The new algorithm dynamically learns the computational power of each processor during an adaptive phase and then schedules the remainder of the workload using a weighted self-scheduling scheme during the completion phase. Different from previous studies, our scheme uniquely considers the runtime effects of block sizes on the performance for heterogeneous multiprocessors. It finds the right trade-off between large and small block sizes to maintain balanced workload while keeping the accelerator utilization at maximum. Our algorithm does not require offline training or architecture-specific parameters. We have evaluated our scheme on two different heterogeneous architectures: AMD 64-core Bulldozer system with nVidia Fermi C2050 GPU and Intel Xeon 32-core SGI Altix 4700 supercomputer with Xilinx Virtex 4 FPGAs. The experimental results show that our new scheduling algorithm can achieve performance improvements up to over 200% when compared to the closest existing load balancing scheme. Our algorithm also achieves full processor utilization with all processors completing at nearly the same time which is significantly better than alternative current approaches.

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Section: Introductionmentioning

confidence: 99%

A dynamic self-scheduling scheme for heterogeneous multiprocessor architectures

Belviranlı

Bhuyan

Gupta

2013

ACM Trans. Archit. Code Optim.

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“…Several alternative implementations for accelerating the Smith-Waterman algorithm using FPGAs ( [14], [15]), vec- tor operations on x86 CPUs [16], and GPUs (e.g., using CUDA [17]) exist. However, because the PaPaRa alignment kernel differs significantly from the standard SmithWaterman implementation, we omit a more detailed review at this point.…”

Section: Related Workmentioning

confidence: 99%

Accelerating Phylogeny-Aware Short DNA Read Alignment with FPGAs

Alachiotis

Berger

Stamatakis

2011

2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines

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Abstract-Recent advances in molecular sequencing technology have given rise to novel algorithms for simultaneously aligning short sequence reads to reference sequence alignments and corresponding evolutionary reference trees. We present a complete hardware/software implementation for the acceleration of a program called PaPaRa, a newly introduced dynamic programming algorithm for this purpose.We verify the correctness of the proposed architecture on a real FPGA and introduce a straight-forward communication protocol (using gigabit ethernet) for seamless integration with the encapsulating steering software that is executed on a PC processor. The hardware description and the software implementation are freely available for download.When mapped to a Virtex 6 FPGA, our reconfigurable architecture can compute 133.4 billion cell updates per second for the novel, tree-based alignment kernel of PaPaRa. Compared to PaPaRa, running on a 3.2GHz Intel Core i5 CPU, we obtain speedups for the alignment kernel, that range between 170 and 471. For the entire application, that is, the alignment kernel and the trace-back step, we obtain speedups between 74 and 118.

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“…Only the configuration of the same read length is compared for fairness. It could be realized from the Table I that [19], [26] need 3.87 and 6.71 times of more time than ours to finish the same workload respectively with the same amount of chip area.…”

Section: B Chip Areamentioning

confidence: 95%

“…A scalable accelerator for comparing the protein sequences is brought forward in [18], which implements the SmithWaterman-Gotoh algorithm and is able to align two sequences of 1024 base pairs. The Mercury BLASTP [19] which is implemented on a workstation with two Xilinx Virtex-II 6000 FPGAs, could obtain a 11-15x speedup over the BLASTP software while delivering close to 99% identical result. Besides, more FPGA-based architectures [20]- [25] are presented in the literatures in recent years for accelerating the read mapping.…”

Section: B Fpga-based Accelerating Solutionsmentioning

confidence: 99%

A FPGA-Based High Performance Acceleration Platform for the Next Generation Long Read Mapping

Chen

Wang

et al. 2013

2013 IEEE 10th International Conference on High Performance Computing and Communications &Amp; 2013 IEEE International Conferen

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To compare the newly determined sequences against the subject sequences stored in the databases is a critical job in the bioinformatics. Fortunately, recent survey reports that the state-of-the-art aligners are already fast enough to handle the ultra amount of short sequence reads in the reasonable time. However, for aligning the long sequence reads (>400bp) generated by the next generation sequencing (NGS) technology, it is still quite inefficient with present aligners. Furthermore, the challenge becomes more and more serious as the lengths and the amounts of the sequence reads are both keeping increasing with the improvement of the sequencing technology. Thus, it is extremely urgent for the researchers to enhance the performance of the long read alignment. In this paper, we propose a novel FPGA-based system to improve the efficiency of the long read mapping. Compared to the state-ofthe-art long read aligner BWA-SW, our accelerating platform could achieve better performance. Experiments demonstrate that for reads with lengths ranging from 512 base pairs up to 4096 base pairs, the described system obtains a 10x-48x speedup for the bottleneck of the software. As to the complete mapping procedure, the FPGA-based platform could achieve a 1.9x-3.2x speedup versus the BWA-SW aligner, reducing the alignment cycles from weeks to days.

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A Banded Smith-Waterman FPGA Accelerator for Mercury BLASTP

Cited by 33 publications

References 8 publications

A dynamic self-scheduling scheme for heterogeneous multiprocessor architectures

A dynamic self-scheduling scheme for heterogeneous multiprocessor architectures

Accelerating Phylogeny-Aware Short DNA Read Alignment with FPGAs

A FPGA-Based High Performance Acceleration Platform for the Next Generation Long Read Mapping

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